What You Need to Know as an Industry Newcomer
If you’re a regular reader of 3D InCites, you’ve probably seen the word “chiplets” before, but you may not know what they are. To put it simply, chiplets are small “chips” that perform singular functions really well, but they can’t perform their designated function on their own. Instead, they are designed to be integrated with other chiplets in a package to perform like a full chip.
For instance, a chiplet may be a processor core, a memory block, or something else, and it needs its companion pieces to work effectively. Because of this, some industry leaders like to compare chiplets to Legos.
Chiplets are becoming an increasingly important part of the advanced packaging conversation. With advancements in artificial intelligence (AI), high performance computing (HPC) and other next-generation technologies, more computing power needs to fit in less space than ever before, and chiplets can help make this possible. So, to learn more about chiplet integration, I spoke with Raj Peddi, director of marketing strategy at Henkel. Henkel is a material supplier for the semiconductor packaging industry.
Peddi explained that chiplets help reduce both cost and time to market, in addition to enabling higher device efficiency. Chiplet integration, he said, is mainly a backend process, as opposed to the standard system-on-chip (SoC) design that gets created during wafer manufacturing. Being a backend process is what helps bring down the cost.
For context, a standard SoC is just a broad type of semiconductor design, and a chiplet architecture is just one type of SoC. Most SoCs encompass all components onto a single piece of silicon at the same technology node. In that way, some parts are using more advanced technology than they need to perform their part of the task. This is what differentiates chiplets. Although they’re designed to work together, they’re built separately at their optimal technology nodes. Then, they’re reintegrated into one device using advanced packaging processes. This is how chiplets are more cost-effective.
Video 1: Demonstrating the process of chiplet integration. Source – Henkel
While chiplets are a function of design, assembling them requires heterogeneous integration. There are several approaches that can be used, depending on the interconnect density of the end-device. Options include fan-out wafer level packaging (FOWLP), 2.5D on an interposer, or 3D stacking.
But, as you can imagine, nothing in the semiconductor industry is ever a one-and-done process. Even with each chiplet performing its role, chiplet integrators need to consider several factors, including the adhesive solutions used to bond each chiplet to the package substrate, or underlying material. Peddi shared that innovations in adhesives are essential for creating new and improved HPC packages that help power AI, autonomous vehicles, and other next-generation applications.
As he explained, some of the materials Henkel uses to improve the package are:
- Low warpage liquid compression molding underfill (LMUF)
- High fracture toughness, low coefficient of thermal expansion (CTE) capillary flow underfills
- Low stress, high elongation lid or stiffener attach materials
Let’s start with warpage. Wafer warpage is a critical issue in FOWLP because it has a direct impact on yield. Managing warpage successfully increases the yield, or the number of “usable” chips that come out of the manufacturing process. When a wafer warps, it reduces its stability and reliability, which costs chip makers valuable time and money if the warpage is enough to render the device defective.
Peddi also explained that stress is a major concern when it comes to chiplet integration. As the size of the package increases to accommodate the computing needs of AI, he shared that larger devices are subject to multiple thermal cycles, which makes the die and the package even more susceptible to warpage.
In addition, he mentioned that it’s not only important to consider the design of the stiffener, but it’s also crucial to think about the material that’s used to attach the stiffener to the package. For a bit of context, a stiffener helps improve the load-bearing ability of the package without increasing its size. It also helps to further reduce warpage.
To conclude, Peddi provided additional insight as to why chiplets are gaining popularity, and why we can expect to see more of them in the future.
“SoC and front-end nodes are becoming expensive and time consuming,” he said. “There are many challenges, like maintaining performance as the transistor size keeps shrinking, and addressing heat dissipation as transistor density increases. Chiplet-style integration addresses most of these challenges, and that’s the reason they are becoming increasingly common for high performance computing applications.”
Henkel recently hosted a webinar focused on the market trends, challenges, and material solutions for advanced packaging. For those who missed the live sessions, a detailed summary of the webinar content is available, along with information on Henkel’s packaging solutions.
