Managing the System-level Netlist and Its Exceptions in 3D ICs
3D IC is a growing semiconductor technology that pushes the limits of single-die designs. Splitting a large die into multiple smaller dies has proven to provide an acceptable yield and reify the era of chiplets, which has elevated IP reuse to new levels.
By placing different dies (aka heterogeneous integration) side-by-side, 2.5D ICs provide even greater value since different process nodes can be mixed in the same semiconductor product. Furthermore, stacking dies in the z-direction, as in true 3D-IC, reduces undesired delays by making the interconnects shorter.
3D IC process technologies like hybrid bonding and direct bonding allow for even shorter interconnects and remove the need for I/O drivers. True 3D IC stacking improves the form factor even more than possible with 2.5D-IC and fan-out wafer-level packaging (FOWLP).
From a system-level design perspective, although each advanced packaging variation (i.e., 2.5D IC using silicon interposers, fan-out wafer level packaging, true 3D IC) offers some unique challenges, some challenges apply to all of them. The designer must ensure that the assembly is physically connected as expected compared to the golden design intent.
Capturing a system-level netlist can be a challenge in the case of multiple substrates since each substrate usually requires a different design team, methodology, and/or format. Since the 3D IC design intent drives system-level LVS verification, the designer needs to ensure that the system-level netlist is golden; that is, it is the absolute reference of system connectivity. To demonstrate what golden means, assume that the designer is running LVS-type verification between the 3D IC assembly layout and the 3D IC assembly system-level netlist. When a connectivity error is reported in the LVS run, the designer should not have to stop and wonder where the issue comes.
Although this undesirable situation might be inevitable in some cases, especially when a new design flow is being introduced and deployed for the first few projects, the goal of a system-level connectivity capture step is to raise the confidence in the netlist as much as possible to the point where it can be considered as a golden/frozen reference.
This white paper explains how to handle the complex challenges when transitioning from traditional connectivity capture flows to advanced system-level flows using an automated approach in which the designer can compare their traditional flow netlist vs the system-level assembly netlist generated from Siemens xSI and Calibre 3DSTACK flow for system-level LVS.
