The National Advanced Packaging Manufacturing Program (NAPMP) is one of multiple CHIPS R&D initiatives that seek to create United States (U.S.) leadership in advanced packaging and provide the technology and skilled workforce needed for packaging manufacturing in the U.S.
NAPMP-funded activities and CHIPS manufacturing incentives seek to establish a self-sustaining, profitable, domestic packaging industry where advanced node chips manufactured in the U.S. and abroad can be packaged within the U.S.
In combination with other CHIPS for America education and workforce efforts, NAPMP-funded activities also seek to produce the capable workforce needed for the success of the domestic packaging sector.
Emerging technologies like high-performance computing (HPC) and artificial intelligence (AI), advanced telecommunications, biomedical devices, and autonomous vehicles require leap-ahead advances in microelectronics capabilities.
In early July, the CHIPS program through the National Institute of Standards and Technology (NIST) put out a notice of intent (NOI) for the NAPMP.
The NAPMP intends to announce a notice of funding opportunity (NOFO) for new R&D activities to establish and accelerate the domestic capacity for semiconductor advanced packaging. The purpose of this NOI is to offer preliminary information to potential applicants, to facilitate partnerships and responsive proposals relevant to one or more of the five highlighted R&D areas:
- Equipment, Tools, Processes, and Process Integration
- Power Delivery and Thermal Management
- Connector Technology, Including Photonics and Radio Frequency (RF)
- Chiplets Ecosystem
- Co-design/Electronic Design Automation (EDA)
Individual proposals may address one or more of the listed R&D areas.
The intended objective of the NOFO is to demonstrate the benefits of R&D results through a combination of prototypes and baseline packaging flows suitable for adoption by the U.S. industry.
The NOFO is expected to set out R&D areas to be supported in addressing key challenges and technology gaps in advanced packaging. It is expected to provide for coordinated R&D efforts aligned through common technical targets so that results collectively contribute to implementable advanced packaging flows.
The NOFO is expected to include a specific opportunity for prototype development in exemplar application areas such as HPC and low-power systems needed for AI.
In designing proposals, applicants should consider in their planning activities the below five program drivers guiding the design of this NOFO.
- Scale-down and Scale-out
- Heterogeneous Integration, including Chiplets
- End-to-End Advanced Packaging Flows
- Prototypes for Demonstrating Functionality
- Aligned R&D efforts for Implementable Advanced Packaging Flows
These program drivers are aligned with industry roadmaps and the objectives outlined in the Vision for the National Advanced Packaging Manufacturing Program.
‘Scaling-down’ refers to shrinking the size of the features on the package and increasing interconnect densities. ‘Scaling out’ refers to increasing the number of chips assembled on the substrate and overall functional density in both 2D and 3D architectures.
The second driver, “Advancing capabilities for heterogeneous integration (HI), including Chiplets”, focuses on the NAPMP objective of creating an advanced packaging ecosystem based on heterogeneous chiplet technology to promote widespread and easy use of the technologies developed. Applicants should incorporate considerations for heterogeneous integration and chiplets-based architectures in their research planning.
“Enabling end-to-end advanced packaging flows” requires flows suitable for industry adoption. The NAPMP aims to “develop packaging platforms capable of high-volume and customized manufacturing.” Applicants should therefore plan to implement their research outputs in a full packaging flow.
“Demonstrating functionality in prototypes” should provide evidence for new capabilities, increased efficiencies, lowered production costs, reduced environmental impact, or other benefits resulting from research advances. The goal here is to enable successful advanced packaging development efforts to be validated and transitioned at scale to U.S. manufacturing. NAPMP expects to support projects to design prototypes in the aforementioned application areas such as HPC and AI, and low-power systems under the NOFO.
NAPMP plans to align R&D efforts so that R&D results are not isolated or incompatible, but instead collectively contribute to implementable advanced packaging flows. Successful applicants should expect to participate in coordination and information sharing across projects in all R&D areas. The NOFO is expected to require coordination and cooperation activities connecting all of the supported R&D projects.
Good luck to all potential respondents.
For all the latest on Advanced Packaging stay linked to IFTLE….
