YES Delivers Multiple VeroTherm Formic Acid Reflow Systems To Leading Semiconductor Device Customers

YES (Yield Engineering Systems, Inc.), a leading manufacturer of process equipment for semiconductor advanced packaging applications, today announced that it has delivered multiple VeroTherm Formic Acid Reflow (FAR) systems to leading logic and memory customers. This system will be utilized to enable 3D stacking of memory and logic chips required to support the growth of high-performance AI accelerators driven by large language model (LLM) applications.

The VeroTherm FAR system is designed to provide solutions for achieving sub-10-micron micro bump structures with fluxless solder and mass reflow processes. This system enables superior quality and total cost of ownership (CoO), particularly for the manufacturing of advanced packaging architectures such as stacked logic and high bandwidth memory (HBM) that are an integral part of the AI accelerators currently being launched in the market.

“The VeroTherm offers a unique single wafer chamber design with flexibility to improve reflow quality and addresses challenges associated with reduced bump pitches. YES has demonstrated superior reflow results with no bump cracking defects observed at sub-30 micron pitch and no collapsed bumps with pitches down to 12µm. The YES proprietary process also results in defect-free solder reflow resulting in high throughput and low CoO. These results can extend bump-based mass reflow technology to sub-10um pitch” said Alex Chow, SVP Global Sales at YES. “These orders are an important milestone for YES as it is a validation of our efforts to serve the multiple market segments.”

According to Saket Chadda, SVP, and GM Dry Business Unit at YES, “Our Verotherm FAR wafer product line offers vacuum-based single-wafer processing with unique capabilities of performing the task of removing oxides and reflowing solder into excellent bump shapes without defects found in older atmospheric pressure systems. It eliminates SnAg agglomerate defects and rough surfaces while minimizing inter-metallic compound zones with extendibility down to sub-10um micron pitches.”