The massive buildout for 5G communications is just getting underway, but its full economic impact – estimated to possibly reach $13.1T and provide 22.8 million jobs – is not expected to be fully realized until 2035. Building on the previous four generations of wireless infrastructure that brought ever higher and more sophisticated levels of wireless communication and data transfer to the world, the grand vision for 5G communications is to bring everyone and everything together including machines, objects, and devices.
Leveraging artificial intelligence (AI) and machine learning (ML) at most points in the network, 5G will enable the buildout of smarter, connected everything – smart devices, smart businesses, smart factories, and sequentially higher levels of autonomous vehicles communicating with, or even guided by, smart cities and infrastructure. It’s expected that when fully completed, 5G will accommodate one million devices per square kilometer and be so fast that remote surgery will become a reality.
5G innovation starts with system IC architecture exploration. Whether it’s designing 5G infrastructure or the many Internet of Things (IoT) edge nodes/devices that connect to the network, developing an ideal IC architecture for 5G infrastructure and applications has many considerations and many routes to success. 5G IC logic design and verification considerations require a complete solution for IC design, verification, and validation of digital front end (DFE), front-haul 5G ICs, and other digital blocks.
5G IC physical design and verification is fundamental to any 5G system, whether it be for 5G infrastructure or 5G edge devices is to optimize for the best PPW. The SoCs designed for 5G infrastructure need to be extremely high-performance to receive, interpret, and then transmit data as fast as possible. At the same time, 5G infrastructure equipment is estimated to consume anywhere from 50 to 68 percent more energy than 4G equipment.
5G requires a new paradigm for PCB collaboration and faster delivery. As the chipsets for 5G infrastructure advance in sophistication to move 5G infrastructure beyond 10GHz/cmWave configurations into configurations with mmWave and MassiveMIMO supporting beamforming, the complexity of the design of PCBs within these systems will also increase dramatically. Design teams will need to implement 5G boards with an increasing number of layers to accommodate not only the routing of massive pin counts of these ICs but also to isolate and shield high-speed digital traces from high-frequency RF circuitry to ensure overall system reliability. Signal integrity and power analysis will become a must-have at every step of the design process.
In this white paper, we highlight how Siemens EDA DISW Xcelerator portfolio, spanning from IC, packaging and PCB/systems electronic design, software design to mechanical design and manufacturing all the way to enterprise-level IC and system running in the field monitoring – are uniquely positioned to help companies deliver differentiated 5G-ready platforms to market.
