IFTLE has been updating our readers on the chiplet market and the technology since I served as subject matter expert (SME) for DARPA’s Dan Green who gets credit for developing the CHIPS program (Common Heterogeneous Integration and IP Reuse Strategies) in 2017. At that time the average packaging engineer couldn’t tell you what a chiplet was.
Program Manager Green pointed out that the CHIPS goal was to develop design tools, integration standards, and IP blocks required to demonstrate modular electronic systems that can leverage the best of DoD and commercial designs and technology. Particular emphasis was placed on trying to develop a technology infrastructure that can be adopted by both the aerospace infrastructure and the commercial infrastructure.
IFTLE 323: “The New DARPA Program “CHIPS” …”
IFTLE 367: “DARPA CHIPS Headlines 14th 3D-ASIP Conference”
IFTLE 396: “DARPA Envisions CHIPS as New Approach to Chip Design and Manufacturing”
We’ve come a long way since then, with the emphasis being maintained on standardizing communication interfaces so chiplets from different vendors can/will be able to communicate with each other.
For those still a bit unsure of what this chiplet technology is all about, we covered that a few months back in IFTLE 545 “Chiplet Definition and Standardization”
With all this activity going on at conferences like IEEE ECTC and IMAPS, it certainly was not a shock when the industry heard that there was going to be a “Chiplet Summit” held in San Jose in late January. The meeting was put on by Semper Technologies, a for-profit company, that has set up several electronics conferences including the Flash Memory Summit.
An initial look at the program left me with mixed reactions. Some of the key technologists in the area were there, but certainly nowhere near all of them. There were also a lot of names I had never heard of presenting (recall I have been covering this area for 7+ years). I will certainly admit that some of these folks were approaching the technology from the chip architecture, and EDA design side of things, and that certainly is not my forte.
While I was not able to attend the meeting, the organizers have loaded all the keynote talks and presentations on their web page allowing access to all interested parties. We thank them for this.
We’ll take a few weeks to look at significant presentations. I’ll start off by saying that some of the keynotes, especially, were very disappointing so you won’t see me covering them here. I was also struck by the fact that Siemens (Mentor Graphics) had (doing a quick scan) at least eight presentations and Synopsis had several also making it, so as I said, it was heavily EDA driven. Let’s take a look at what some of the key speakers had to say.
Yole Group Looks at the Chiplet Market
Hackenberg and Lorenz from Yole Group took an in-depth look at the chiplet market.
They first defined what they meant by a chiplet:
“A Chiplet is a discretely manufactured physical piece of hardware designed to be integrated in the manufacture of a heterogeneous integrated circuit so that the completed IC is functionally equal to or greater than that of a complete system designed on a single monolithic die. The chiplet is physically or economically optimized to perform a specific functional and interoperable subset of the complete heterogeneous system IC.”
A chiplet is commonly manufactured in a process suitable for the physical and economical attributes for its function.
- This includes wafer characteristics, process geometry, material, size, cost, and other attributes.
- The chiplet platform can be suitable for the integration of application processor cores, coprocessors, sensors, transceivers, memory, storage, interfaces, and other subsystems. It could include something other than a silicon-based die so long as its function becomes intrinsic to the final system-level IC. In theory, chiplets could be integrated in stages such that two or more highly interrelated functions combined to make a larger chiplet.
The term chiplet is currently only applied when the die is integrated into an IC constituting a complete heterogeneous system IC.
- Most ICs identified as chiplets will be uniquely suitable to systems-on-chip (SoCs) or systems-in-package (SiPs), including those functioning as microprocessors, applications processors, field programmable gate arrays, coprocessors and similar heterogeneous processors.
- No design restriction is assumed to say that a physical product could not also perform its function discretely as a companion chip on a board or module.
- The term chiplet does not apply to the discrete use case, only the integrated IC use case. The value of the term is in focusing on the integration processes (before and after integration), high-end die-to-die communications, physical and logical restrictions, and other characteristics required of a subsystem in a system IC comparable to a monolithic die.
They view the value of the overall chiplet market as a function of the market for all ICs made in a chiplet process!
- Even though the main benefit is improved yield, it provides a path forward for expanded optimization, fewer tape-outs, improved product line efficiency, and industry diversity.
- The market value of the chiplet platform mainly benefits the SoC/SiP chip supplier.
The Processor Market
Seven companies make up >90% of the overall processor revenue. Of these companies, Intel, AMD, and Apple, Marvell, and IBM have brought implementations of chiplets to market. Thus far, the chiplets brought to market have been mainly the in-house, proprietary kind, where the solution contains only chips from one vendor, using in-house IP or that of a manufacturing partner.
With even the narrowest definition of chiplets, Yole finds a market for chiplet-based processors in excess of $135 billion by 2027. By 2032, they expect chiplet adoption will accelerate in consumer and automotive markets, and gain a foothold in defense, aerospace, industrial, and medical, leading to a TAM of chiplet-based ICs in excess of $205 B.
High-end performance packaging, with some of its platforms incorporating chiplets, is expected to pick up more market share in the coming years reaching 39% in 2027 up from 24% in 2021 as shown in Figure 3.
Yole reports that the value of the chiplet platform is not just in the value of the semiconductor die or the advanced packaging services. It is in its contribution to extending the economics of Moore’s Law for generations to come
The UCIe™ Consortium
Brian Rea of Intel gave a presentation on the UCIe™ Consortium.
UCIe™ (Universal Chiplet Interconnect Express™) aligns the industry around an open platform to enable chiplet-based solutions.
UCIe Consortium is incorporated. It currently has 90+ member companies with six working groups working on evolving technology. Intellectual Property Rights (IPR) protection is in place for members. Board members are shown in Figure 4.
UCIe 1.0 Specification has been ratified to provide a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing that will enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoC. The new open standard establishes an open chiplet ecosystem and ubiquitous interconnect at the package level. There’s more to come in upcoming posts.
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