Over the past 10ish years, there has been a great deal of debate about the longevity of Moore’s Law. The reshoring of semiconductor manufacturing to the United States has put Moore’s Law back on center stage. There are a group of folks. including Jensen Huang CEO of Nvidia, who recently stated Moore’s Law is Dead. Then on the other side of the Law, there is Intel’s management, TSMC, and IMEC, who keep promoting that Moore’s Law is alive and well and continue to try and shrink the transistor and back end of the line (BEOL) every 2 years.
Both sides of the discussion continue to shrink the transistor, each using its roadmap for the next generation of transistors. Below is the IMEC version of the roadmap, which takes the industry from FinFETs to Gate All Around (GAA) to, fork sheet then CFET transistors. All of these advances keep shrinking the transistor and moving the industry down Moore’s Law.
Simply stated, Moore’s law has the number of transistors per unit area doubling every two years. Figure 2, showing the transistor density over time using the Apple M1 chip as the latest example, would suggest that the industry is still on the Moore’s Law track. Adding to the debate around Moore’s Law is the transition to 3D packaging, which has the potential to increase the number of transistors per unit volume, by 2x or more as the packaging technology evolves and the chip stacks go higher.
Whether or not you are on the side of Moore’s Law is alive or Moore’s law is dead, technology is still evolving at a rapid pace across the chip industry. One of the showcases for semiconductor technology is taking place this week (December 5-7, 2022) in San Francisco, at IEDM 2022. The title of this year’s conference is; The 75th Anniversary of the Transistor, and the Next Transformative Devices to Address Global Challenges”.
One of the key technology trends according to the IEEE IEDM 2022 press release is the strong and growing use of 2D materials. The successful use of 2D materials will be crucial to the roadmap above for improved speed and transistor performance. TSMC will be presenting a paper on the world’s first 2D gate-all-around (GAA) device, from TSMC et al. The successful implementation will extend the GAA technology for a generation or two.
In the area of 3D integration, there are sessions on heterogeneous integration and System in Package (SiP). Session 3 leads off this focus area, with A*Star, TSMC, ASE, Intel Unimicron, and Samsung discussing the merits of substrate technology on advanced packaging. It will be nice to see how the technology is maturing and to see the different aspects of all the major players in the 3D packaging space.
One of the comments surrounding 3D packaging is the lack of standards for chiplet integration. What similarities in roadmaps will be discussed, and while standards are forming, will there be one set or multiple sets of standards?
While 3D packaging is one aspect of 3D growth, the transistor itself is also undergoing a significant transformation. Above we have discussed 2D materials in the 3D GAA. There are multiple sessions on developing the transistor of both the near and distant future. These incorporate both the structures shown in Figure 1 and new material development in both 2D gates, as well as in the transistor itself. Forksheet, CFET, and atomic channels all appear to be on the agenda for the week. How close is the industry to the implementation of these technologies, and who appears to be leading in getting these structures out of the lab and into manufacturing?
Another aspect of the 3D structure is the back end of the line (BEOL) metallization. Improving the performance of the BEOL is critical to reducing the heat and power consumption of the more advanced chips. This is typically accomplished by improving the resistivity of metals and lowering the capacitance of the dielectric. More and more air gaps are finding their way into the dielectric stack to improve BEOL performance. Historically, logic has been the focus of BEOL discussions, but several memory papers are looking at improving the BEOL performance using new techniques.
While it might not be the coming out party for quantum computing at IEDM 2022, there is a keynote on quantum computing by LETI. This is followed up by a special focus segment in session 14, where the audience will hear six papers on different aspects of quantum computing. While this technology is still in its infancy some programs will let you work with the quantum computers that are in existence to begin developing expertise. IBM recently announced a 433 Qbit quantum computing chip. I’m looking to see how fast this technology can develop, as it can open some new doors in the area of computing.
As always IEDM has something for every aspect of the spectrum of the electronic device. There are multiple sessions on memory, with several papers on ferroelectric materials for the capacitor. We will also hear about the smallest most energy-efficient MRAM. Power Semiconductors from SiC devices to silicon bipolar transistors are also on the docket. If you did not attend in person, there is still an on-demand program that starts on December 12, which you can still sign up for here.
While the 75th anniversary of the transistor is something to celebrate since 3D InCites also has a strong focus on diversity we are celebrating the IEDM announcement that for the first time in the IEDM’s long and storied history that the top three spots on the IEDM 2022 Executive Committee are held by women: Barbara DeSalvo of Meta Platforms is the General Chair; Dina Triyoso of TEL Technology Center America is the Technical Program Chair, and Kirsten Moselund of Paul Scherrer Institute/EPFL is the Technical Program Vice Chair.” Congratulations to all from 3D InCites.
