Chaired by 3D InCites Community member Steffen Kröhnert of ESPAT Consulting, the Electronics System-Integration Technology Conferences (ESTC) series is a premier venue for academics and industry to present and discuss the latest developments in assembly and interconnection technology and new applications. This year, the event is being held in Sibiu, Romania from Tuesday, Sept 13-16.
There is a full program of keynotes, technical tracks and workshops, including exhibitions and professional development courses. Of course, several 3D InCites community members will be in attendance and here are some of the highlights of where you can find them.
Keynote 3-3 – CNF-MIM Technology, Enabling the Worlds Thinnest Capacitor
Maria Bylund, Smoltek AB, Gothenburg, Sweden
This keynote will present a novel technology (CNF-MIM) combining Carbon Nanofiber (CNF) materials and MIM (metal-insulator-metal)-like technology, enabling capacitors with total thickness lower than 40 µm suitable for use in future miniaturized electronics. The ultra-thin and discrete CNF-MIM capacitors have been manufactured and characterized on several substrates, showing excellent electrical properties such as high capacitance density of several hundreds of nF/mm2 , ESR (equivalent series resistance) in the mOhm range, low ESL (equivalent series inductance) on the order of 10 pH thus being promising for a multitude of applications within the semiconductor industry. To assess the long-term durability, CNF-MIM capacitors have also been subjected to prolonged exposure to high temperature and constant voltage bias environments following a HTS (high temperature storage) and BTS (biased temperature stress) standard. The CNF-MIM capacitor show initial robustness against degradation in these scenarios.
Keynote 3-5 – Advanced Packaging: Enabling a New Generation of Silicon Systems
Mark Gerber, Sr. Director, Engineering & Technical Marketing, ASE, Inc.
Demand for new efficiencies in the semiconductor design and manufacturing process is propelling the increasingly vital role of packaging to deliver on requirements related to miniaturization, power and performance. During his presentation, Mark will explore heterogeneous integration and chiplet innovation, and describe how advanced packaging technologies are enabling highly complex system integration, which is required to create a smarter and more sustainable world for generations to come.
Mark Gerber heads engineering and technical marketing in his capacity as Senior Director at ASE.
Keynote 5 – About the mission of Siemens Digital Industries Software
Oren Manor, Siemens Digital Industries Software, Tel Aviv, Israel
Siemens Digital Industries Software is driving transformation to enable a digital enterprise where engineering, manufacturing and electronics design meet tomorrow. Our solutions help companies of all sizes create and leverage digital twins that provide organizations with new insights, opportunities and levels of automation to drive innovation. For more information on Siemens Digital Industries Software products and services, visit sw.siemens.com.
Oren Manor has been the Siemens Opcenter Core Business Director at Siemens Digital Industries Software since October 2021, where he manages the overall business strategy for the Digital Manufacturing portfolio for the Medical, Electronics and Semiconductors Industries.
Professional Development Courses
PDC A – Why is now the right time to start digitalizing electronics manufacturing with an end-to-end holistic solution?
In this course, we will explore the key global trends impacting the Electronics Manufacturing and PCB Assembly Industry and the challenges that they bring to manufacturers – including the global shortage in components, dramatic increase in PCB complexity, significant increase in New Product Introductions (NPIs) and Product Revisions and decrease in lot sizes up to “lot-size-one”. We will demonstrate why digitalization of the electronics factory is the most effective solution to many of these challenges and why building a holistic end-to-end digitalization strategy can provide the most significant return-on-investment (ROI).
The PDC will also cover the topics, which have been described in the following e-book, white papers and webinar sessions:
- Siemens_ebook_Oren Manor_Advanced-Manufacturing-In-the-Digital-Age-2nd-edition_tcm27-97004.pdf
- Siemens-SW-(Mike Santarini)-Digital-transformation-How-Siemens-EDA-helps-you-engineer-a-smarter-future-faster-83731-WP-C5.pdf
- Siemens-PLM-Smart-manufacturing-for-electronics-WhitePaper_tcm27-57766.pdf
- Siemens-SW-A-comprehensive-digital-twin-for-PCB-assembly_WhitePaper_tcm27-64886.pdf
- Digital twin webinar series _ Jay Gorajia.docx
- Siemens-SW-Driving-engineering-for-vehicle-electrification-WhitePaper_tcm27-93397.pdf
Instructor
OREN MANOR, Siemens Digital Industries Software, Tel Aviv, Israel
ESTC 2022 schedules some Special Workshops.
Hot topics in the field of electronic packaging are presented and discussed. Share experiences and opinions with colleagues.
Workshop 5 – Heterogeneous Integration Roadmap (HIR) Workshop, organized by William (Bill) Chen, ASE
Bill Chen holds the position of ASE Fellow & Senior Technical Advisor at ASE Group.
Exhibitors
ASE
ASE’s VIPack™ is an advanced packaging platform designed to enable vertically integrated package solutions. VIPack™ represents ASE’s next generation of 3D heterogeneous integration architecture that extends design rules and achieves ultra-high density and performance. The platform leverages advanced redistribution layer (RDL) processes, embedded integration, and 2.5D and 3D technologies to help customers achieve unprecedented innovation when integrating multiple chips within a single package.
ERS
ERS electronic’s ProbeSense® is a patent-pending temperature calibration device allowing automatic and highly accurate measurements below 30mK in the actual probing area, and consists of a temperature sensor, which is mounted in the probe card position on the prober. Taking advantage of the XYZ axis motion capability of the prober, the sensor can measure the temperature over several points on the wafer surface in the same conditions as during wafer probing. ProbeSense™ is delivered with adapter plates to fit your prober of choice and is thereby compatible with all wafer probers in the semiconductor industry.
Evatec
Evatec’s wafer platforms that process up to 300mm formats feature highest levels of throughput, support the use of long life targets and are equipped with a unique degassing technology that achieves best in class contact resistance and layer uniformity performance required in WLCSP, FOWLP and 2.5D/3D devices. FOPLP applications and next generation IC substrate technologies are supported by Evatec`s market leading CLUSTERLINE® 600 equipment platform. The design and concept of the panel based PVD equipment platform is based on the field proven wafer platform, and is capable of processing substrate sizes up to 650 x 650 mm, delivering highest levels in outgassing performance, layer adhesion and stack uniformity.
KLA
KLA’s extensive portfolio of packaging solutions accelerates the manufacturing process for outsourced semiconductor assembly and test (OSAT) providers, device manufacturers and foundries for a wide range of packaging applications. Innovations in advanced packaging, such as 2.5D/3D IC integration using through silicon vias (TSVs), wafer-level chip scale packaging (WLCSP), fan-out wafer-level packaging (FOWLP) and heterogeneous integration as well as a wide range of IC substrates create new and evolving process requirements.
Xperi
Xperi Corporation and its brands DTS, IMAX Enhanced, HD Radio, and Invensas, are dedicated to creating innovative technology solutions that enable extraordinary experiences for people around the world. The Invensas semiconductor technologies can be found in DRAM memories, image sensors, RF devices, MEMS sensors, processors and mixed signal devices currently in high volume production at leading original equipment makers (OEMs), original design manufacturers (ODMs), and integrated device manufacturers (IDMs). Invensas DBI® Ultra is a die-to-wafer hybrid bonding 3D interconnect technology platform that makes it possible to manufacture 4, 8, 12 or 16-high 3D stacked memory while meeting the stringent packaging height and performance requirements for next generation high-performance computing.
