As I listened to keynote speakers and panelists at the recent 2022 IMAPS Advanced SiP Conference talk about the commercialization of chiplet technologies, I felt a sense of déjà vu. The key takeaways of the talks and panel discussions sounded eerily familiar. And then it hit me: these were the very same conversations we had when silicon via (TSV) and hybrid bonding processes were in their infancy. Heck, even the conversation about how chiplets are just another word for multi-chip-modules (MCMs) recalled the same argument we’ve had over and over again about system-in-package (SiP). I’ve now been around long enough to understand the parallels between the adoption of 3D IC technologies and chiplet architectures.
Will Chiplet Adoption take 20 years?
Bob Patti, NHanced Semiconductors, reminisced about the early days of 3D stacked DRAM, and how what he had thought would be a 3–5-year journey to commercialization turned into 20 years. Is that what we are looking at with chiplets? Will they be stuck in high-performance applications until the costs come down, EDA tools are developed, and test methods are figured out?
I would like to think not. Rather, it seems the lessons we learned in bringing 3D IC technologies from concept to commercialization paved the way for faster adoption of chiplet architectures. Let’s look at some of the reasons why it took so long for 3D IC technologies to be adopted.
First, many 3D approaches were developed before the industry needed them. They were a technology looking for an application. Moore’s Law was still very much viable in the early days of through silicon via (TSV) development. The power, performance, area, and cost (PPAC) benefits of 3D ICs and wafer-level packaging approaches had yet to be proven. Because no new technology is adopted until there is no other way to achieve performance goals, they sat on the back burner. So until the cost of TSVs came down, these then-emerging technologies were relegated to high-performance (HPC) applications.
As a result, the IDMs and foundries continued to chase nodes. They hadn’t yet discovered the paragraph in Gordon Moore’s paper that stated at some point, we would have to heterogeneously integrate disparate functionalities to continue along with Moore’s Law roadmap.
In his keynote talk, Chidi Chidambaram, Qualcomm, called on the room to increase efforts to reduce the cost of chiplet architectures so that they could be used in high-volume mobile applications, and not just fill the HPC application needs like servers and 5G networks. It was the same story as before when Qualcomm pushed the industry to lower the cost TSVs and then opted for fan-out solutions instead. Then and now, the emerging technologies were too expensive for Qualcomm’s pocketbook for mostly mobile applications. As a fabless company, it seems like they are still looking at advanced packaging as a cost adder rather than the value add that it has become.
Second, 3D IC development happened along the same linear path as previous generations of technologies:
- Develop and prove the processes
- Use what design tools existed and adapt by hand
- Wait for volumes to increase to develop EDA tools
- Develop test last
Third, the downturn of 2009 nine delayed the need and adoption of TSV technologies. While development continued in earnest (because what else can you do during a recession)? Adoption was stalled.
Fourth, the parallel development of fan-out wafer-level packaging eclipsed 3D ICs as a more affordable, interim solution to stacking with TSVs to achieve the PPAC needs of driver applications. Again, as long as there was a cheaper way to do it, the adoption of TSVs and other 3D integration technologies had to wait.
Chiplets vs MCMs – A Design Paradigm Shift
But times have changed. Even Intel is acknowledging that Moore’s law is running out of steam. That’s why they’ve invested in advanced packaging. The same goes for AMD and TSMC. Because scaling to smaller nodes is so costly, they’ve realized that it’s time to look at it from a system level, and suddenly advanced packaging adds value. But I’m wondering why Qualcomm still doesn’t see it that way? Chidambaram’s keynote was focused on a shift to system-level technology co-optimization (STCO), yet the main message was about the need to standardize processes and drive down cost. I did question Chidambaram about this in our podcast interview. Listen below to it to see what he says.
Another key indicator that we are approaching the commercialization of chiplets differently than we did 3D IC is the involvement of EDA vendors from the get-go. When an IMAPS SiP Conference panel on chiplets includes a representative from a traditionally front-end EDA company like Synopsys, you know things have changed. For years, Synopsys avoided investing in the advanced packaging space, leaving it to Siemens and Cadence. But with chiplets, they are fully on board.
Although some industry veterans continue to insist otherwise, chiplet architectures are not merely your grandparents’ MCMs with a new marketing spin. While the concept of integrating chips of different functionality into one SiP may be similar, the methodologies are vastly different. Interconnects using TSVs and hybrid bonding, vs wire bond, flip chip, and thermocompression bonding allow for considerably higher density and shorter distances. The chiplets themselves are designed to work in concert with other chiplets and can’t function as a single chip on its own. It’s not a package design approach, it’s a disaggregated system-on-chip(SoC) design approach. As John Park of Cadence recently explained to me, when we used to talk about package co-design, we were talking about package-board co-design, and the EDA tools being adapted originated in PCB design. For chiplet architectures, we are looking at chip-package co-design, with the new EDA tools adapted from front-end tools.
My main takeaway from the IMAPS SIP Conference was an appreciation of lessons the microelectronics industry learned from the 3D IC journey. It’s promising to see that we might be able to move forward with chiplets more rapidly and it won’t be another 15 years before they find their way into consumer applications.
