Next week the top global event for Advanced System-in-Package technologies comes to Sedona. Combining the 3D ASIP and IMAPS SiP events into an all-in-one comprehensive program, IMAPS established the Advanced System-in-Package conference to focus exclusively on innovative SiP technology developments, solutions and business trends. Advanced SiP 2022 will be a high-end event that combines the IMAPS System-in Package Conference and the 3D ASIP Conference. Advanced SiP 2022 will offer cutting-edge presentations from scientists, technologists and business leaders across the globe in cellular, IoT, automotive, computing and networking market segments.
As the official Podcast for IMAPS, 3D InCites’ Francoise von Trapp will be onsite at the conference once again recording her “Are You Listening” podcast episodes. Any interest in starring in or sponsoring an episode, let us know. Many of our community members will also be in attendance. Here are their highlights:
Monday, June 20th
Heterogeneous Integration Roadmap (HIR) Workshop 9:00am-12:30pm
The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics identifying technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration between industry, academia and government to accelerate progress. The roadmap offers professionals, industry, academia and research institutes a comprehensive, strategic forecast of technology over the next 15 years. The HIR also delivers a 25-year projection for heterogeneous integration of Emerging Research Devices and Emerging Research Materials with longer research-and-development timelines. The HIR is sponsored by three IEEE Societies (Electronics Packaging Society, Electron Devices Societry & Photonics Society) together with SEMI and ASME Eeelctronics & Photonics Packaging Division.
HIR Agenda:
9:00 am – 9:15 am
HIR Session Introduction: Mark Gerber, SiP General Chair and Bill Chen HIR Introduction
9:15 am – 9:40 am
HIR Overview
Bill Chen, ASE
10:05 am – 10:30 am
Automotive Electronics
Vikas Gupta, ASE
11:50 am – 12:15 pm
HIR Workshop Final Question & Closing Remarks
Bill Chen, ASE
PDC 2: System-in-Package (SiP) – System Solutions Through Miniaturization
Mark Gerber, ASE US, Inc.
This PDC course will introduce the package platform SiP (System-in-Package) and how some companies are diversifying from SOC (System-on-a-Chip) to leverage heterogeneous silicon integration and package miniaturization to enable system level solutions. A short market perspective will be reviewed as well as how industry segments are leveraging SiP and how the OEM market is evolving and creating system level ecosystems to enabling content revenue- a key area of IOT.
| Tuesday, June 21st |
1:30pm – 2:00pm
Empowering Front-End Cellular Innovations with Advanced SiP Solutions
Curtis Zwenger, Amkor Technology
2:30pm – 3:00pm
Innovative Materials for Advanced Packaging and System in Package (SiP)
Szi Pei LIm, Indium Corp. (Dongkai Shangguan)
4:00pm – 5:30pm
Panel Session:
REMAINING CHALLENGES IN THE ADOPTION OF 5G
Moderator: Jan Vardaman, TechSearch International
Wednesday, June 22
10:45am – 11:15am
Advanced Fanout Embedded Bridge Packaging Technology for Chiplets Integration
Lihong Cao, ASE Group
11:15am – 11:45am
Hybrid Bonding – A Key to the Future
Robert Patti, Nhanced Semi.
3:30pm – 5:00pm
START-UP COMPETITION
Moderator: Jan Vardaman, TechSearch InternationalStart-up Companies:
Averatek
Avicena
Mosaic Microsystems
Sivers Semiconductors (Mixcomm)
The start-up competition session will feature brief presentations by each of the four start-up companies listed above, which will be evaluated by a panel of selected judges and a winning company will be selected during this live session.
Mosaic’s David Levy will be highlighting its core bonding technology, Viaffirm, an advanced temporary bond approach in which thin glass interposer wafers can be attached to conventional handles such as glass and silicon. Mosaic’s Viaffrim enables thin glass substrates to be processed with seamless integration into existing manufacturing streams. It is resistant to etching and cleaning chemistries, and most importantly allows processing at temperatures exceeding 400C. Mosaic is developing technology to best commercialize the full capabilities of Viaffirm, including a wide range of via morphologies, via fill approaches, and methodologies for creating multilayer complex glass structures for antennas and interposers.
5:00pm – 6:30pm
Panel Session on
HIGH PERFORMANCE COMPUTE & SILICON PHOTONICS
Moderator: Eelco Bergman, ASE Group
Panelists:
Lihong Cao, ASE Group
Kenneth Larsen, Synopsys
Khai Nguyen, nVidia
Robert Patti, Nhanced Semi.
Thursday, June 23rd
Session 5: EDA/Design
Chair: Curtis Zwenger, Amkor Technology
9:00am – 9:30am
Design and Analysis Challenges for Multi-chiplet 3D Integration
John Park, Cadence
Session 6: Test / Inspection
Chair: Habib Hichri, Ajinomoto
10:45am – 11:15am
Test Impact of Chiplets in Packages
Warren Wartell, Amkor Technology
You can find the full schedule of events here
