Advanced packaging technology enables continued performance scaling across applications, and it is clear that the coming generations of mobile and edge computing, cloud computing, and distributed high-performance computing will require heterogeneous chip integration technologies. To accommodate demanding performance and scaling requirements while also meeting stringent technical specifications for speed, bandwidth, power delivery, and thermal management, leading-edge devices will depend on multiple passivation layers and redistribution of metal routings to connect the various chips.
One of the world’s largest mobile phone companies adopted wafer fan-out PoP packaging technology back in 2016 to address these issues and not surprisingly, additional companies have been following suit. Another mobile phone giant has announced that it is developing its version of FO-WLP for mobile applications, while simultaneously working on yield improvement and cost reduction with the use of panel fanout.
As wafer fanout technologies evolve, several of our customers are starting to adopt interconnect bridge technologies, which offer several advantages. By providing high density, the bridge allows relaxed feature sizes for redistribution layers (RDL) and improves yield. Using a bridge can also allow a reduction in the number of RDLs, thereby reducing the cost of the package. Concurrently, the package size is also evolving. While the most common substrate package size is still 35x35mm, we have seen next-generation multiple chip integrations with package sizes as large as 150x150mm.
To stay ahead of the technology curve, we at YES work in close partnership with our installed base of semiconductor industry leaders, ensuring that our products meet their current and future technology needs, both for smaller form factors and high-performance applications with larger areas supported by high-density laminate and glass-based substrates. Toward that end, we are working on issues such as solder reflow in reducing environments for small pitch BGA and ensuring that our panel-based VertaCure™ and VertaBond™ systems address the unique surface enhancement needs of larger substrates.
As a further step in our ongoing mission to enable our customers’ roadmaps, we recently acquired Semiconductor Process Equipment Corporation (SPEC) of Valencia, CA – a highly-regarded manufacturer of wet processing equipment. SPEC’s high-volume electroless plating systems for under-bump metallization, along with its decades of expertise in critical advanced packaging technologies like electrolytic plating, will enable YES to maintain our leadership in enhancing surfaces and materials for our customers’ applications.
We predict that chip-to-chip interconnects, performance, form factor, and power delivery demands will continue to drive the adoption of RDL-based solutions, and we look forward to meeting the challenges of this exciting era for advanced packaging.
