Here at Siemens EDA, we expect to see greater emphasis in several areas of semiconductor package design as we head into 2022. To start, heterogeneous integration (HI) of multiple dies into system-in-packages (SiPs) will be common across all market segments and will use multiple integration platforms, not just silicon interposers, as is common today.
These complex multi-die/chiplet designs will see a greater use of hardware description language (HDL) driven flows, which speed up system definition and debug cycles compared to today’s schematic-driven approaches. As these HI multi-die/chiplet SiPs grow in size and complexity, the adoption of system-level design rule checking (DRC) and layout versus schematic (LVS) verification will become mandatory to avoid fabrication and manufacturing assembly errors and their corresponding negative impact on costs and delays.
As HI-using chiplets start to become common, almost mainstream, we expect to see the emergence of a robust supply chain of commercial off-the-shelf (COTS) chiplets containing what was previously available as soft/hard IP, as used in monolithic SoC designs. In addition, as HI SiPs become more mainstream, we will see the emergence and adoption of alternatives to silicon as an integration substrate. Organic-based interposers will deliver the wiring density and electrical/thermal performance needed for many target markets and, of course, enable larger sizes, due to no reticle limitations and lower costs.
As HI grows in usage and its available integration platforms increase, the number of die/chiplet integration permutations, or scenarios, will also grow. As a result, issues around thermal and electromechanical stress will become pervasive and will need to be understood and addressed earlier in planning and prototyping to prevent them from becoming a key problem should the wrong integration scenario be selected and moved into detailed implementation. This will drive the use of early predictive thermal and stress analysis, ideally during the planning and prototyping process, in addition to the current early SI/PI analysis. This early analysis will enable the semiconductor packaging team to identify and qualify acceptable integration scenarios and reject unacceptable scenarios.
The final area in which we will see greater focus into the next year is test. Reliance on known-good die or chiplets (KGD) by itself will not be sufficient to ensure functional performance and reliability. These designs will require the adoption of more comprehensive test strategies capable of addressing the new test challenges presented by such 2.5D/3DIC SiP designs—and by test, we mean complete, system-level test that will include the active and passive devices as well as the integration substrates and any embedded active or passive devices within them.
We expect many aspects of semiconductor package design will be considerably different sooner than later. Some will be completely new, and others will have grown or matured in their use, driven by complexity demands. In addition, an ecosystem around the supply and standardization of chiplets will have emerged, enabled by exchange formats such as those being created by the Open Compute Projects Chiplet Design eXchange (CDX) format, which will provide the catalyst for broad adoption of HI across all market segments, beyond the handful of mega IDMs/fabless and systems companies who currently have access to this capability.
