Santa Clara’s Convention Center was home to DesignCon 2019 from January 29-31, 2019. This conference is well known for showing printed circuit board (PCB) and system designers the latest technology advances, enabling higher performance and lower power and lower cost solutions. Bootcamps, tutorials, keynotes, and many in-depth technical sessions offered engineers up-to-date information to make their jobs easier and their designs more competitive.
Off to Boot Camp
On Tuesday, one of the all-day boot camps focused on machine learning (ML). A number of experts in this field conveyed ML principles and explained numerous techniques for combining human intelligence and big data analysis to improve the results of a wide range of design and manufacturing processes. In addition to the many technical messages, the presenters also highlighted ML contributions of these Center for Advanced Electronics Through Machine Learning (CAEML) members:
Two other all-day boot camps focused on power integrity (PI) and signal integrity (SI) respectively. Eight half-day tutorials addressed topics important for high-speed PCB designers and rounded out the broad range of educational sessions for the mostly younger crowd – compared to this gray-hair blogger.
Since 2008, my professional focus has been on advanced IC packaging technologies. DesignCon 2019 confirmed in my eyes the value higher levels of integration offer board and system designers. 2.5/3D-IC solutions reduce not only PCB space needed but also the number of connections between PCBs and the need for power-hungry SERDES links. They shrink systems’ form-factors, weight and manufacturing cost. These facts are now widely recognized because DesignCon 2019 no longer focused on the traditional tag-line “Where the chip meets the board”, but also offered a number of sessions addressing “Where the die meets the package meets the board”.
Where the Die Meets the Package
For example, I attended three technical sessions that exclusively addressed advanced packaging topics. In his presentation, Youngwoo Kim, a post-doc researcher at KAIST’s Terabyte Interconnection and Package Lab, compared the performance benefits of high bandwidth memories (HBM) on interposers with other design solutions (Figure 2).
Kim suggested using statistical methods to more accurately analyze signal integrity of randomly switching HBM signal lines on a wide bus. He demonstrated this method’s accuracy, by comparing the results with lengthy transient simulations using HSPICE.
In another session on Wednesday morning, Bo Pu, on behalf of a Samsung engineering team, presented how to minimize coupling and noise in the more than one thousand signal and power lines interconnecting logic and a High Bandwidth Memory (HBM 2) device on an interposer (Figure 3).
Figure 3: High-speed memory I/O path: The silicon interposers provides a signal transmission with fine-pitch from logic die to HBM. High Speed I/O serial path: A silicon interposer with through silicon vias (TSV) acts as the platform for the transition of signal or power between die and package. (Courtesy of Bo Pu, Staff Engineer at Samsung Electronics)
Pu also discussed how to accurately model interactions between TSVs as well as signal and power traces. He presented analysis results of mixing ground and signal lines, the impact of changes to the ground plane in the interposer, and how varying spacing between lines change the eye of the resulting signal. Pu warned that above 10 GHz, insertion loss in silicon interposers gets very high and significantly dampens signals.
In another advanced packaging session, Samsung and Cadence jointly presented a sign-off reference flow, including these major steps:
- In the planning step, a feasibility check and simulations of chip-package-board constraints are essential
- During the actual multi-die design, PI and SI effects of the high-speed interface between logic and memory especially need to be analyzed
- The entire design and all interactions between the components need to be simulated top-down before sign-off quality is reached and a transfer to manufacturing makes sense
In many other sessions, I enjoyed hearing brief references to the benefits of interposer-based (2.5D) designs. Design experts from Xilinx also presented interposer-related topics in sessions I had to miss.
5G and Cars that Fly
Like most conferences, DesignCon 2019 offered impressive keynotes too. Tuesday’s keynoter, UC Berkeley Physics Professor Irfan Siddiqi, talked about the promise of quantum computing and the benefits and challenges qubits offer. Considering that this topic is rather new to me, allow me not to report about it and refer to the 5th amendment – my right to decline self-incrimination.
Professor Robert Heath from UC Austin delivered Wednesday’s keynote, focused on 5G technology and vehicle-to-all-surroundings ( V-to-X ) communication.
He explained that 5G technology offers both higher bandwidth and shorter latency, compared to today’s 4G networks. Depending on the application, Heath stated that 5G is already deployed or may take several more years to be rolled out due to remaining challenges. For example,5G needs a very large number of base stations, efficient unidirectional beamforming, its high-frequency signals are unable to penetrate walls and others.
Thursday’s keynote speaker was Gloria Lau, the head of Hardware Engineering at Uber. She started her presentation by describing the Uber Air program and their goal to enable us to travel like the Jetsons. For readers who did not grow up in the U.S. (like me), you can learn about this iconic cartoon here, and even watch the complete first season on Amazon Prime.
After giving the audience something to dream about when stuck in 2D traffic (Figure 5), Lau impressed us with numbers that demonstrate the rapid growth and success of Uber. With it, she laid the groundwork for outlining the challenges her team must deal with to serve customers and keep Uber’s many data centers all over the world running.
Recognizing that personal transportation will experience many changes in future, the DesignCon organizers announced DRIVE, a new conference and expo focused on innovation in this space. The first one will be held at the Santa Clara Convention Center from August 27 to 29, 2019.
I got the impression that compared to previous years, DesignCon 2019 much more clearly conveyed that PI and SI are major challenges for board and system designers. These topics must be a key reason why the advanced packaging sessions, which explained how to use interposers to mitigate these challenges, were so well attended.
EDA Suppliers That Get It
On the exhibition floor about 200 companies, among them most major EDA vendors, attracted the attention of conference attendees. Ansys, Autodesk, Cadence, Dassault, Keysight, Mathworks/SiSoft, Mentor – a Siemens Business – and Simberian showed how they make advanced package, board and (sub) system designers more productive.
Just like other recent conferences I attended, lots of new opportunities as well as new challenges were addressed. In this context, I would like to invite you to hear about and discuss with me on Wednesday, February 13, during a MEPTEC Luncheon at SEMI in Milpitas, major new challenges and opportunities for our industry. Check it out, here, and join us, please!
Congratulations to all DesignCon organizers and contributor. Great Conference! Allow me just one suggestion for DesignCon 2020: As more of the IC value creation is moving from the dice to the (multi-dice) package and PCB experts are analyzing how and where to reduce board space and system cost by utilizing advanced packages, please consider expressing these important trends with a new DesignCon tagline: “WHERE THE DICE MEETS PACKAGE AND BOARD”. —- See you again at DesignCon 2020, January 28 to 30, in Santa Clara. ~ Thanks……Herb
