I cannot believe 3D InCites is already turning 10! As wise people say, time flies! Taking a step back, I have to admit a lot of progress has been made since my first attendance as a young engineer to the EMC 3D workshops back in 2008. At that time, we were discussing how to form a via, how to fill it, how to use a temporary wafer carrier to process thin wafers…etc.
We are definitely more mature now (not old!) and I’m convinced 3D InCites contributed to the progress by sharing knowledge across the industry. I’m honored to have been part of their advisory board since 2010 under the enthusiastic leadership of Francoise. Hereafter is my simple analysis of our 3D journey so far…
The birth
This maybe not considered ‘3D integration’ by many people (including me) but the CMOS image sensors (CIS) that use via-last through silicon via (TSV) interconnect technology were a very significant step in the commercialization of 3D. The Industry started to discover layers could be stack on top of each other with direct connections, and with much higher performances than die stack using wire bonds. This was the starting point.
The teenage years
Stacking memory dies and application process engines in high-end cell phones (now known as smartphones) was identified as potential killer application to deliver high bandwidth at lower power consumption and with very small vertical dimension. However, thermal budget constraints and business model/supply chain limitations killed the high hopes. Hopefully Xilinx and AMD made them in a slightly different way. However, the volume they manufactured cannot be compared to how things would have been if a flagship smartphone manufacturer had decided to embark on using wide IO memory with processor. In the meantime, cell phones started using TSMC’s integrated fan-out (InFO) in a package-on-package (PoP) configuration, which was already a great achievement with significant benefits.
The young adult
Endless opportunities await 3D integration. I still believe that system-on-chip (SoC) disintegration with IP blocks designed at their optimized technology nodes and then stacked on top of each other could happen. This is the next step after the new system-in-package (SiP) development we see now and it should be part of the heterogeneous integration roadmap. The recent announcement of Intel’s Foveros in December 2018 confirms this is likely happening. Let’s see what 2019 brings to us!
