DARPA Envisions CHIPS as New Approach to Chip Design and Manufacturing

First a word on the change in venue…

After working with Pete Singer at Solid State Technology from 2010-2018 and previously at Semiconductor International from 2007 – 2010 (as PFTLE), I have decided to move my packaging blog, IFTLE, to a new platform. I will be forever indebted to Pete for giving this old school technologist a chance to report on, and share his thoughts on, the world of IC packaging.

After I left SST, Francoise approached me and offered me the 3D InCites platform. I quickly envisioned the conversion of “Insights from the Leading Edge” to “InCites from the Leading Edge” and the play on words seemed like a natural.

So…… I hope all of my IFTLE readers will find their way here and will continue to find tidbits of useful information in my reporting on leading-edge IC packaging and the changes occurring in the IC world that underpin it.

It’s all about the CHIPS

As a first blog, I was asked by management to address the DARPA Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program, for which I serve as a subject matter expert. CHIPS is a perfect example of the impact of packaging in the post-Moore’s Law world in which we now find ourselves.

As I detailed previously in IFTLE 323, the CHIPS vision is an ecosystem of discrete, modular IP blocks, optimized for manufacturing in the appropriate node, which can be assembled into a system using existing and emerging interconnect technologies (Figure 1).

Modularity and reusability of such IP blocks will require electrical and physical interface protocols to be standardized and widely adopted by the community supporting the CHIPS ecosystem. The CHIPS program hopes to develop the design tools and integration standards required for modular, integrated circuit (IC) designs.

CHIPS was initially developed under DARPA MTO program manager, Dan Green, and is now being run by its program manager, Andreas Olofsson.

The CHIPS program is part of DARPA’s Electronics Resurgence Initiative (ERI), which will involve investments of roughly $200M annually over the next four years. ERI is seeking to develop “…an electronics community that mixes the best of the commercial and defense capabilities for the national defense”.

The stated goal of CHIPS is to:

Establish and demonstrate common interface standards
Enable the assembly of systems from modular IP blocks built with these established standards
Demonstrate reusability of the modular IP blocks via rapid design iteration

In concept, the different functionalities and blocks of intellectual property can be fabricated into small chiplets, which then can be mixed, matched, and combined onto an interposer, “akin to joining the pieces of a jigsaw puzzle” (Figure 2)

Figure 2: DARPA’s CHIPS concept and motivation.

The dozen prime contractors selected to kick off the program in August of 2017 included large defense companies (Lockheed Martin, Northrop Grumman), large microelectronics companies (Intel, Micron), semiconductor design players (Cadence, Synopsys, Intrinsix, and Jariet Technologies), and University teams (Michigan, Georgia Tech, and North Carolina State).

While it is hoped that CHIPS will lower cost and decrease turn-around time for military electronics, it is also hoped that the design flows that will be created will have a major impact on the industry as a whole. As such, DARPA actively sought the participation of the commercial electronics world and included Intel and Micron as active, financially supported participants.

Standardizing the Electrical Interface – Intel AIB

During the first 12 months of the program, the participants have coalesced on Intel’s Advanced Interface Bus (AIB) as their low-power die-to-die electrical interface (Figure 3). AIB reportedly features a one-Gbps-per-lane SDR transfer rate for control signals and a two-Gbps-per-lane DDR transfer for data. AIB is process and packaging technology agnostic. Intel currently uses AIB for its Stratix 10 FPGAs. Other participants of the CHIPS program will be using the interface in their specific chiplets.

Figure 3: An example of a possible heterogeneous system in package (SiP) that combines sensors, proprietary ASIC, FPGA, CPU, Memory and I/O using AIB as the chiplet interface [Ref: Intel]

What about the Physical Interface…the Footprint?

Ahh….this is where the packaging comes into play. Since it is obvious that the chiplet-based solution will require more I/O than a monolithic solution, most practitioners envision µbumping to a high-density silicon interposer as a requirement (Figure 4). In that way, CHIPS hopes to piggyback on the technology developed over the last decade for 2.5D/3D IC.

Figure 4: Chiplet assembly on a silicon interposer.

Right now, some favor copper pillar bump and some favor gold-gold thermo-compression (TC) bonding for forming the interconnect. I personally favor the former (since Au is traditionally not used for forming the interconnect in the digital silicon world) with a migration towards direct copper-copper TC bonding as that technology matures, and the temperature and pressure requirements hopefully lessen. Whichever is eventually chosen, physical footprint standardization will be required to ensure the assembly compatibility of the chiplets. Chiplet designs are underway and we should be getting early results from CHIPS in Q2-Q3 2019.

Who will manufacture the chiplets? Who will supply the silicon interposers? The DoD understands that its low-volume requirements do not present the most interesting business opportunities for traditional foundries and OSATS and that such suppliers are not currently US-based.

Will US sources develop as the program shows the technology has technical and economic advantages? It is certainly hoped that commercial sources like Intel and Micron see the advantages of the technology and adopt them for commercial products, which will increase the likelihood of their availability for the DoD, But only time will tell!

IFTLE promises to keep our readers updated. ~ Phil