As you all may know, in most fan-out wafer level packages (FOWLP) such as embedded wafer level ball grid array (eWLB) by Infineon and STATS ChipPAC, and TSMC’s integrated fan out (InFO), the chip(s) are embedded in epoxy molding compound (EMC). Additionally, in some fan-out panel-level packaging (FOPLP) such as those being built by Fraunhofer IZM and J-Devices, the chip(s) are embedded in EMC. Other companies, such as AT&S, Unimicron, and Imbera, are embedding chips in a laminate organic substrate.
In my opinion, in general, chips that are embedded in a laminated organic substrate cannot be larger than 5mm x 5mm, due to the thermal expansion mismatch between the silicon chip (2.5×10-6/oC) and the organic substrate (15×10-6/oC – 18×10-6/oC).
On June 28, 2013 (priority date: March 5, 2013), Maxim Integrated filed a patent (US 20140252655 A1), for an invention by Khanh Tran, Arkadii V. Samoilov, Pirooz Parvarandeh, and Amit S. Kelkar, “Fan-out and Heterogeneous Packaging of Electronic Components,” proposing to embed the chip(s) in a silicon substrate (Figure 1). A paper was presented during the IMAPS International Conference.
Again, my opinion is that, in general, the size of the chip cannot be larger than 4mm x 4mm (or the size of the silicon package cannot be larger than 5mm x 5mm). This is because of the thermal expansion mismatch between the silicon (package) substrate (not the chip) and the PCB (18×10-6/oC).
On May 31, 2017, at IEEE ECTC, George Institute of Technology (GIT) will present an alternative to EMC, organic laminate, and silicon, by presenting the very first demonstration of chips embedded in a glass substrate for FOPLP (Figure 2). The paper represents a collaborative effort by GIT, Schott, Asahi Glass Co., Ltd., and DISCO Corporation.
Will this glass fan-out (GFO) technology popular? I cannot tell. But, at least, it adds a new direction in fan-out packaging! ~ J. Lau
