The era of “More than Moore” was alive and well in 2016 as the semiconductor industry witnessed many new developments in advanced packaging. Among these was the production of the first hybrid bonded image sensor, which enables high-performance image processing as well as on-sensor memory to provide faster extraction and processing of images. As this image sensor technology enables an entirely new set of capabilities, we expect further adoption of stacked image sensors in consumer, automotive and household devices. The device design and layout will progress from row/column connection with via-last toward hybrid bonding.
The key to the adoption of hybrid bonding is the ability to reduce the pitch of the hybrid bond pads. Today, the size of hybrid bond pitches is in the 6-8-micron range, requiring the connection of an array of pixels between the two stacked image sensor layers. To support the drive to higher resolution and performance capabilities, the industry must achieve even smaller pitches to the point of single-pixel connection using hybrid bonding. This will require new technology implementation to further reduce the overlay alignment of wafer bonding.
Stacked image sensors are only one of many applications that can be greatly enhanced through hybrid wafer bonding. Successful deployment here can pave the way for hybrid bonding into leading front-end semiconductor fabs supporting a variety of new applications. Already we are witnessing the development of stacked DRAM, which is driven by the need for high-performance computing to support high-speed memory-intensive applications such as data mining, physics simulation, and modeling. Here, temporary bonding is currently the bonding method of choice. However, as the stacked memory market continues to grow and create demand for greater levels of device performance, manufacturing will shift from chip-level stacking to hybrid wafer stacking driven by the achievement of a nearly ten-fold pitch reduction with hybrid bonding, which in turn will enable up to a 5,000-fold increase in pitch connections, compared to today’s stacked thin dies.
Looking ahead to 2017, we expect “More than Moore” to continue to play a leading role in moving the semiconductor industry forward. As device scaling continues to slow down and become increasingly complex and costly to implement, advanced packaging provides the most promise in driving performance forward. For example, die partitioning – separating various semiconductor device functions from a single large device into smaller dies – will continue as a means to both increase yields and reduce fabrication costs. Wafer stacking technologies will be increasingly important in supporting these fan-out packaging architectures, such as systems-in-package (SiP). This trend is also seen in other complex devices such as new image sensors, MEMS devices or multi-purpose SiPs where the computation and data processing is done directly in the device. Wafer bonding will again be key to driving these advances in stacking technology, where specialized carrier solutions will be mandatory to manufacture these devices. ~ Thomas Uhrmann, Director of Business Development, EV Group
