Is Moore’s Law dead or not? It depends on your perspective. Last week at ECTC 2016, Rozalia Beica, Dow Electronic Materials, gathered a prestigious group of senior executives from the world’s leading microelectronics research institutes to discuss Life after Moore’s Law. Panelists included Marie-Noelle Semeria, CEA-Leti; Dim Lee Kwong, IME; Luc van den hove, imec; CP Wong, NCAP; and Subu Iyer, UCLA CHIPS. Each discussed the strategy they will pursue to continue innovations for next-generation computing technologies, with or without Moore’s Law. All but imec said efforts would be focused on packaging.
“Moore’s law has ended many times,” noted Semeria, “But we (CEA-Leti) are still alive, and the space for innovation is wider than ever.” She said that the real end of Moore’s Law began two years ago when we reached 28nm and the cost started to go up. But she said that the computing engine continues, and will reinvent itself into a “cognition engine” focused on function integration and energy efficiency.
Semeria described the roadmap for high-performance computing (HPC) as undergoing shifts in integration, technology, and architecture. At Leti, this has involved 3D integration comprising interposer-integrated chiplets with photonic links. By 2020, there will be a technology shift in memory materials including 3D VLSI and high-density 3D integrated Si photonic dies and neuromorphic materials for advanced chiplet architectures. Computer architecture will shift to quantum or neuromorphic architectures.
The Internet of Things (IoT) will feed HPC, because of the high rate of data we have to manage, noted Semeria, citing the latest trends in sensing, data fusion, connected health, artificial intelligence, deep learning, Big Data and cloud computing as evidence of this. “Knowledge will be key to handling the Data Economy,” she said.
Leti’s strategy is based on a system approach focused on miniaturization, connectivity, and security to support HPC, servers, µservers, connected health, etc. “Each application points to its moon,” noted Semeria, “It’s a broad space for innovation and requires a broad portfolio of technologies and skills to fix a solution.” Leti’s “moons” include photonics, advanced interposer, smart packaging, RF, and nanowires. Leti has achieved nanowires that are 3nm in diameter, which can play a role after 5nm.
Offering IME’s perspective and strategy, Kwong started out by noting that while IME has been benchmarking against imec and Leti for years, “I just met them tonight for the first time,” indicating Semeria and Van den hove. At IME, whatever the strategy, Kwong said they have to make sure the technology can be commercialized, as they are government-funded. He also talked about a paradigm shift to heterogeneous integration for system scaling. “Packaging has not scaled much in the last 40 years compared with transistors,” said Kwong. “Scaling the package will drive the next generation.” This includes fan-out, multi-die, and even the aforementioned neuromorphic chip.
IME’s strategy for solution-based IoT involves developing hardware and software integration for system design enablement. Kwong talked about IME’s Science Park 11, where they work on More-than-Moore technologies, and have a 300mm development line for 2.5D, 3D, and fan-out wafer level packaging (FLOWLP) processes. Additionally, Fusionopolis is a 300mm industry joint lab for advanced lithography, WLP, metrology, and more.
Wong and Iyer echoed the previous speakers sentiments that the future is about system integration using advanced packaging processes. Wong explained that this is the reason NCAP was formed in 2012, to bring advanced packaging to China. The center has established programs for 2.5D integration, fan-out wafer level system-in-package (FOWLSiP). This includes MEMS chips with through silicon vias (TSVs.)
With regard to CMOS scaling, Iyer is on the same page as Kwong. He says the biggest problem we have today in the hardware world is that Moore’s Law is an economic draw. Everything is based on cost-per-transistor. “If you can’t scale the chip, scale something else,” he said. “Nothing in the history of civilization has scaled so fast as silicon. But package and board features have scaled modestly. This is the focus of his work at UCLA – to scale the package. I have written previously about the CHIPS program Iyer launched in November at UCLA. To recap – the goal is to develop an app-like environment for hardware that can:
- Cut time-to-market by 5-10x
- Cut NRE cost by 10-20X
- Allow extreme heterogeneity including extensions to cyber-physical systems
- Develop a sophisticated manufacturing workforce
Since the launch, Iyer reports that they are in various stages of an agreement with 10 partners, and have received seed money from DARPA. SO they are well on their way to success in their first phase.
The only panelists waving the Moore’s Law Lives flag was Luc Van den hove, CEO imec. The institute is dedicated to extending Moore’s Law. “We believe that is the essence of what we have to do,” said Van den hove. He talked about meeting recently with Gordon Moore, and presenting him with a lifetime achievement award. “Yes, it becomes more difficult to get the same performance improvements from previous nodes. But there are solutions out there to extend Moore’s legacy,” he added. “Scaling not only will continue, it has to continue to keep momentum in this industry.”
He added that scaling will need a different approach. It will have to “morph” with added techniques to increase complexity. For example, there will be a transition from finFETs to horizontal nanowires, eventually to vertical nanowires, which will bring us to 3nm node or further, and “will keep us (imec) busy for the next decade.” It will require cost-effective technology enabled by EUV lithography. 2D will eventually slow down, and we will have to compensate by combining 2D with 3D technologies. He also talked about 3D heterogeneous integration, quantum computing, and cell stacking approaches like Crossbar and 3D NAND, all of which require innovation across the supply chain. “We have to bring together skill sets to push and extend Moore’s Law.” That imec is focused on these technologies isn’t surprising, as their work is generally very early stage research and development at the concept stage. While they still work on optimizing 3D TSV processes for lower cost, the most exciting work has been already done.
What can the industry do to help these institutes reach their goals? Semeria called for the industry to accept its share of the roadmap. At the same time, researchers need to be more interested in solving industrial challenges. Van den hove seconded that, saying that companies higher up the food chain need to be more involved in new research. The industry also needs to take a longer-term view with regard to packaging, which has up until now been relegated to the bottom of the food chain. For at least the next few years, until new solutions to scaling can be figured out, packaging will clearly be in the driver’s seat. ~ F.v.T.
