As an integral part of the established integrated circuit (IC) supply chain, Outsourced Assembly and Test (OSAT) companies offer IC packaging services on the open market, independent of the chip manufacturer or foundry. OSATs are a subset of the total worldwide IC packaging market, since some IC package assembly is still performed in-house at integrated semiconductor manufacturers (ISM). However, both fabless design houses and ISMs alike use the services of OSATs. Companies with their own packaging facilities use OSAT companies for work beyond the capacity of their own plants, and also for specialty packaging. Unfortunately, OSAT companies are usually the “tail end of the whip”—they often take the brunt of business swings in the semiconductor market. When the economy is down, semiconductor manufacturers will fill up their own packaging plants before contracting the work out to the OSATs, who can then be left with less work. Conversely, when the market is up, the OSATs’ plants are filled to overflowing. The result is that swings in the semiconductor market can have an accentuated effect on OSATs.
To achieve a more stable and profitable business model, many OSATs are investing in cutting-edge packaging technologies, allowing them to consume a larger percentage of the overall worldwide IC packaging market over time. One of the more interesting opportunities for OSATs is interposer and 3D packaging. While the value and benefits from advanced interposer and 3D die packaging have been validated in a number of established designs, the adoption of these design techniques is still relatively narrow and limited. One of the reasons these techniques have not yet reached mainstream is the lack of vetted and qualified process design kits (PDKs) for interposer and 3D designs. In the foundry world, PDKs help speed adoption by providing designers with the setup configuration and data files required by their design tools and the foundry process. They also lower risks, because a foundry will stand behind its delivered PDKs with support for and guidance on their use.
However, by definition, interposer and 3D design assemblies contain multiple die in a single package, and these die can each be based on different process technologies, and may come from different foundries. Currently, design teams working with interposer and 3D products waste valuable time establishing their own design methodologies and tool sets, often in a vacuum, missing out on the experiences and best known practices of others in the supply chain. To make interposer and 3D integration a more efficient and less risky process, we need a assembly-level PDKs to augment existing foundry PDKs. Such a PDK would include, for example, information on how to place the dies, rules for routing between dies, DRC style checks for die-to-die alignment, rules for connection verification, materials and thickness information for use in parasitic extraction, and thermal analysis information.
Unfortunately, this is not an easy task. Adding to the complexity, there are many different approaches used to implement multi-die packaging: interposers, multiple die-to-die stacking approaches, package-level routing between die, and the newly-announced embedded silicon bridge technologies. With all the different approaches and suppliers in the design flow, where would such a PDK come from, and how can it be validated?
This could be a great opportunity for OSATs and packaging houses to incorporate best practices into qualified PDK’s for their offerings, providing a foundry-like model to their customers to achieve more reliable results. Customers need an integration platform that can assemble and optimize complex (multiple die and interposer based) packages, and tools that are flexible enough to adapt to new packaging technologies as they emerge. Specific tools and flows will depend on the mode of packaging their customer’s design environments. Delivering this capability requires the OSATs to step up to a new level of sophistication, similar to what foundries have done to support their customers. They need to supply more definitive characterization of their processes and offerings and compile this information into a PDK-like format.
Today, some suppliers are responding to customer demand, but in general, OSATs have not yet embraced this approach as a competitive advantage. To complement and assist the OSATs, EDA vendors need to collaborate with them to determine how their process characterizations can be incorporated into design tools that support the customer. Although the package PDKs could potentially come from the EDA vendors, that would lock customers into a single tool solution, so it would best for the OSATs to provide “vendor neutral” PDKs for their processes. Package-level PDKs would not replace foundry (die-level) PDKs, but rather supplement them with the additional information needed for assembly.
In addition to the PDKs themselves, OSATs could also help customers by providing “how to” information to help them take best advantage of the services they offer. For example, the challenge in testing has more to do with using the right methodologies during design to ensure that a multi-chip product can be tested thoroughly and efficiently. This type of support might be categorized as best practices, and would be similar to the reference flows that foundries qualify for their customers. In fact, qualified reference flows for all aspects of the OSAT’s services would be a boon to many IC designers, especially ones in emerging economies, or those moving up to more advanced technology nodes, or to specialty processes like MEMS or silicon photonics.
These ideas have already moved beyond speculation, as Mentor Graphics and others have started working with OSATs to define commercial assembly PDKs and tools that can use them to provided advanced design capability for 3D-IC designs. Nevertheless, there is still a significant amount of work to be done, so consider this a call to action for the industry and supporting industrial and academic research institutions to work on the needed technologies. For example, we need better models at the package level for mechanical and electrical stress effects, electro-migration, electrical breakdown, thermal behavior, signal integrity and coupling, parasitic effects and other phenomena. We also need ways to certify PDKs and reference flows, and to ensure they are interoperable across suppliers. A lot of this can be modeled on the successful approaches pioneered in the foundry industry—it’s more a matter of vision and initiative. We’re convinced this is the most flexible and efficient approach, so the market should reward first movers who grab the ring. ~ J. F.
