Interposer designs and 3D ICs shift a significant part of the value creation to material vendors and assembly/test houses. It’s only logical that Françoise von Trapp, in her role as Queen of 3D, moderated a high-profile 3D panel this week at the International Wafer Level Packaging Conference (IWLPC), at the DoubleTree Hotel in San Jose, CA. The panelists represented a cross section of our industry: Rama Alapati from GlobalFoundries, Jan Vardaman from TechSearch International, Bob Patti from Tezzaron, Mike Gianfagna from eSilicon, Bel Haba from Google, and Simon McElrea from Energous Corp.
How to also engage the large audience that filled every chair in the Oak Ballroom at the DoubleTree? Of course, Francoise did it in a really high-tech way. She deployed a browser-based polling application, Kahoot.it, accessed by the attendee’s mobile devices so that they could submit their votes in real time. The polling results were displayed in real-time on the conference screen, thereby providing the panelists with a baseline of audience opinion from which to launch discussion. Let’s use these questions to structure the summary of this lively panel:
Question 1: Is system integration with interposers and 3D-ICs outside the current packaging capabilities?
31 people in the audience voted YES, 44 replied with NO. The panelist gave a range of answers that basically said: It’s not only the packaging capabilities that are needed for system integration. We also need 3D design tools to bridge the gap between system needs and packaging capabilities as well as a supportive, knowledgeable and risk-mitigating supply chain and proven building blocks for successful interposer and 3D IC designs.
Question 2: Does fan-out wafer level package (FOWLP) and embedded die meet high-density requirements faced by system integration designers?
The vote was fairly even, with 35 voting “yes” and 31 voting “no”. The panelists had a lot to say about this topic. Initially they focused on FOWLP currently rather wide line/space pitches of 10/10µm as too wide for meeting current requirements and highlighted that cost-effective solutions with 2/2µm will be needed; feature sizes that silicon interposers can offer today. Several panelists emphasized that power dissipation (pJ/bit), latency (psec), and bandwidth (GB/sec), are also important criteria for success. Other comments made clear that not every function integrates well with other functions in a FOWLP. Another, very compelling point was raised: Multi-core CPUs can only provide higher performance if the bandwidth to sufficiently large memory is available; otherwise many cores will be idle while waiting for data to come back from the memory. Lastly, Bob Patti shared a very important observation he made with us: Packaging is no longer an afterthought, IC-Package CO-design is important to get to a competitive solution.
Question 3: Do Interposer and 3D IC designs offer a value add over traditional packaging processes?
The audience opinion was overwhelmingly in the affirmative with 45 voting “yes” and only 9 voted “no”. Vardaman was skeptical and asked right away: At what price? Then she made clear that interposers and 3D ICs will not replace all of our traditional packaging technologies. This led McElrea to quip, “older packaging technologies never die, they just lose their margins!” Several panelists stated that the rush to smaller and smaller feature sizes doesn’t make sense for many applications and smaller companies. They called for a change to the industry’s mindset that places value on the dis-integration capability. Modularity interposer designs offer much more. Patti confirmed this need for change; noting that many customers utilize TSVs to connect dies in older technologies very efficiently and effectively to meet system requirements. Alapati agreed and listed other capabilities, like power dissipation, performance, form-factor as important success criteria, not only feature size. Everybody recognized that we are dealing with a very complex ecosystem for interposer and 3D IC designs, and that many times business considerations are equally if not more important than technology topics.
Question 4: Have interposer and 3D technology challenges been overcome?
13 “yes” votes and 36 “no” votes clearly showed that the audience did not think so. Nor did the panelists. Alapati emphasized that there is a big difference between manufacturing engineering samples and cost-effective (high-yielding) volume production. “We need more market demand to move from low volumes to cost-effective volumes!” noted McElrea. Glass interposers are a perfect example of this challenge. Glass offers lower cost than any other material and is perfect for very high frequency applications, but nobody is willing now to invest in the needed capabilities for processing glass wafers, panels or rolls, because market demand does not (yet) guarantee sufficient return. Silicon interposers are much more costly (2 cents/mm², said Patti), but easy to process with the existing equipment. Even organic interposers (at about 1 cent/mm², according to Patti) are more expensive than glass (will be when accepted). Unless Si interposers offer added value by integrating passives, they’ll be replaced with organic material or glass, depending on application requirements. Patti’s opinion over all is that organic interposers would handle the needs up to 5µm line and space, and active Si interposers would provide the solution for 2µm and below; with the added value of the active devices making up for the added cost of Si. Neither Patti nor Vardaman held out much hope for the glass interposer market due to investment required in establishing the infrastructure vs. the return on that investment.
Question 5: Can 3D ICs offer a viable solution to SoC complexity?
36 voted “yes, only 5 said “no”. With so much agreement there was no ensuing discussion.
Question 6: Cost is what’s holding up adoption of 3D ICs in consumer products.
30 attendees agreed with this statement, while 11 disagreed. The panel agreed that cost is a critical factor for consumer applications and currently not attractive for such cost-sensitive applications. They also stated that memory cubes prices – from Samsung, Micron and SK Hynix – are trending lower and become compelling for more and more applications. As some of these interchangeable memories already demonstrate industry-wide standards and multi-sources help to lower cost and increase volumes. As proven in many situations before, a killer application for interposer designs and/or 3D ICs would drive market adoption. Nobody on the panel or in the audience raised Internet of Things (IoT) devices as a possible killer app.
Question 7: Should customers be willing to pay a higher price for interposer and 3D IC packaging?
An almost evenly split audience with 21 YES and 16 NO triggered some discussion and concluded that if these designs can offer a higher value than traditional 2D ICs, they clearly can and will justify higher prices. McElrea pointed out that the fingerprint sensor on the iPhone 6 is a perfect example for the value of this very secure function, costing $12 and being deployed in very high volumes.
As the panel wound down with the final two questions, much of what had already been discussed was re-affirmed. The statement: system-level cost savings of implementing 3D ICs make it a lower cost alternative to 2D SoC had the audience split 22 to 14 in agreement with this statement. 22 members of the audience agreed that the hold-up to 3D is the design community’s hesitation to use 3D, while 15 disagreed. The panel pointed out that while tools exist, they are not yet user-friendly and the industry is still very risk-averse.
Overall, the panel was well received and sparked some interesting side discussion. von Trapp quizzed the panel on whether they thought forming a new consortium focused on packaging and assembly processes, as was recommended at last week’s GIT 2014, could accelerate low-cost interposer solutions? Ultimately it’s believed that cost will come down organically, and that it wouldn’t happen because of a consortium. ~ Herb
