Lithography Challenges for 2.5D Interposer Manufacturing

In recent years, 2.5D packaging has quickly gained acceptance as an advanced packaging process, and the first products using this technology are now coming to market.¹ Most estimates project growth for 2.5D interposer packaging faster than the industry as a whole. Similar to the multi-chip modules (MCMs) of the past, 2.5D packaging processes use an interposer with vias connecting the metallization layers on its front and back surfaces between multiple silicon dice and a System-in-Package( SiP) substrate (Figure 1). 2.5D packages using high-density interposers can be a cost-effective, high-performance alternative to significantly more complex 3D or SOC integration schemes.

Lithography is a key component of 2.5D integration; however the requirements for interposer exposure systems differ significantly from the requirements of front-end lithography tools. In particular, 2.5D lithography faces specific challenges in regard to resolution, overlay, sidewall angle, exposure field size, depth of focus, warped substrate handling, and backside alignment. As with all middle- and back-end processes, interposer manufacturing must be extremely cost efficient and high yielding.

LITHOGRAPHY CHALLENGES

Resolution
Current resolution requirements are in the single digit micron range. The need for submicron resolution is not anticipated in the foreseeable future. A suitable lithography system should offer an N/A of 0.1 to 0.15 to meet the line/space (L/S) resolution requirement while also preserving a reasonable depth of focus.

Overlay accuracy
Overlay is a combination of stage accuracy and repeatability; alignment microscope capabilities; translation, rotation, and magnification compensation. As a rule of thumb, overlay accuracy should be about one third of the resolution limit of the optical system. For interposer applications with a resolution limit of 2µm, overlay accuracy should be 0.7µm or better. Full-field exposure systems as well as 1x steppers are typically limited in overlay accuracy, mainly due to their inherent inability to compensate for magnification errors. A single-sided telecentric 2x reduction lens combined with a six axis reticle positioning system (Figure 2) enables optimum overlay, including the compensation for real-time variations such as those caused by thermal expansion.²

Sidewall angle and CD control
When processing thick photoresist or photo-definable dielectrics, well-controlled sidewall angles are a critical requirement, and in some cases, a challenge. Although sidewall angles are primarily a function of the photosensitive material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Real-time accurate focus control across the wafer or substrate is required to achieve tight CD control and consistent sidewall behavior.

Depth of focus (DOF)
One of the most important reasons why sub-micron front-end lithography systems, such as DUV steppers and scanners, are not suited for interposer manufacturing is their limited DOF; a design tradeoff of the high numerical apertures required to resolve features measured in tens of nanometers. Without a DOF in the 10µm or greater range, patterning the thick layers used in 2.5D integration is challenging at best.

Exposure field size
The exposure field size (sometimes referred to as field of view (FoV) is yet another important parameter for interposer manufacturing. The size of the exposure field should at least cover the full desired interposer. Although it is possible to stitch multiple exposures together, stitching is inherently slow and imposes a significant throughput penalty. Although there are no standard interposer sizes, they tend to get larger as they combine and interconnect more chips and passive components. Figure 3 compares the number of exposures required to expose a 35mm X 35mm interposer over a 300mm wafer on two commercially available exposure tools having different field sizes. Not only is the number of exposures doubled, but a substantial time penalty must be added for alignment and stitching with the smaller field size.

Infrared alignment capability
Interposers have through-via interconnects from the top side to the bottom side. The lithography step to define via locations must be referenced to the other side of the wafer or substrate—so-called front-to-back alignment. In the case of silicon, an infrared microscope is required to look through the substrate and see backside features.

Warpage
Double-side processing causes substantial substrate warpage that front-end lithography systems are not designed to handle. Their limited depth of focus adds to this problem. Equipment solutions with warped handling features such as switchable and compliant vacuum gaskets on chucks and handlers are needed for lithography and other processing steps. Equally important is real-time “on-the-fly” focusing which adjusts the wafer position at each exposure to obtain optimal focus (Fig 4).

Figure 4: “On-the-fly” focusing, which adjust wafer position in real time to obtain optimal focus at each exposure, and large depth of focus are both essential to handling the thick layers and warped wafers found in 2.5 packaging processes.

COST CONSIDERATIONS
In front-end photolithography processes, where square die first met round wafers, there is an inherent inefficiency near the wafer’s edge, where squeezing as many die as possible onto the wafer inevitably results in part of the exposure field falling uselessly in the exclusion zone or off the wafer entirely. With an appropriately-sized rectangular substrate the rectangular pattern from the mask can fit perfectly, ultimately increasing the average number of interposers per exposure and thereby, the throughput of the exposure process. Likewise, using a larger substrate also increases throughput by reducing the non-productive time spent exchanging substrates. Moreover, the same considerations that have historically driven increases in wafer size should also apply to non-round, non-wafer substrates, potentially providing substantial gains from using large panels throughout the manufacturing process.

In an effort to understand the potential economic benefits, we constructed a model to compare the throughput of a 650mm X 550mm rectangular substrate lithography process with a 300mm wafer lithography process. Details of the model, including the assumptions used, are available here.³ The most obvious advantage in the rectangular substrate process accrues from a more than 5X reduction in the number of substrate exchanges required, resulting primarily from the larger size of the substrate. Less obvious, but also important, are two different “square peg in a round hole” effects. The first is a decrease in the number of exposures required and the second is an increase in surface utilization, both of which result from the better fit between the rectangular field and the rectangular panel. In all cases, the rectangular substrate process demonstrated approximately 2X (die/interposers per hour) throughput advantage over the wafer process. Cost-of-ownership calculations predicted as much as 40% reduction in lithography cost per die/interposer for the large rectangular substrates (Figure 5).

Fig. 5: Comparison of cost per die/interposer for three different exposure tool/substrate combinations at two different doses. — Figure 5: Comparison of cost per die/interposer for three different exposure tool/substrate combinations at two different doses.³

CONCLUSION
2.5D packaging is a novel implementation of an already well-established concept that used to be referred to as MCMs. A high-density interposer is used to efficiently interconnect two or more chips. From a lithography perspective, the manufacturing of these interposers poses some unique challenges, such as resolution, overlay, sidewall, DOF, exposure field size, infrared alignment and substrate warpage. Addressing these challenges calls for lithography equipment technology that is specifically geared towards this application.

From a cost perspective, moving from round wafers to rectangular substrates saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of five. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on round wafers, panel-based processes can reduce lithography cost per die/interposer by as much as 40%. It goes without saying that such a move towards rectangular substrates is only possible for non-silicon materials as Si wafers are inherently round.

Clearly, there are many aspects of larger rectangular substrates that must be addressed before these processes gain broad acceptance. It is worth noting that panel lithography is not new. It is widely used in related industries, such as the manufacturing of flat panel displays and photovoltaic solar panels. The potential economic benefits of panel-based lithography are significant. The model discussed here evaluates relatively modest sized panels. Larger panels may offer even greater benefits. The transition to panel-based processes for advanced packaging applications bears serious consideration.

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