Samsung’s 3D V-NAND Flash Product – The Spires of El Dorado?

Finally! After a year’s worth of guesswork, Samsung’s 3D V-NAND Flash cell has been revealed.

Thanks to the expertise of Chipworks we can see how the memory array looks in the 86 Gbit 32-layer 2^nd generation V-NAND. Figure 1 shows Chipworks’ beautiful cross section. My intention here is to explain the structure, compare it with what I have written about before and, of course, give my opinion.

Previously, I had guessed at the cell size and structure based on Samsung’s ISSCC February 2014 presentation about their 128 Gbit 24-layer 1^st generation V-NAND. Then, Samsung introduced their SSD 850 Pro containing their 86 Gbit 32-layer 2^nd generation V-NAND. It took detective work by others to allow me to guess at their cell size and structure.

Figure 2, taken from my previous article, shows the derived cell sizes and structures from information thus cobbled together.

Well, now we have the real cell structure thanks to Chipworks. How does it compare with the guesswork? Figure 3 shows a generic vertical channel 3D NAND based on Chipworks’ cross section. The wordlines are shown in the same direction as in Figure 2 for ease of comparison (in other words, sweeping from bottom left to top right).

If you need a reminder on how such a vertical channel 3D NAND works, have a quick glance at my first series of blog posts.

On first inspection, Samsung’s product version V-NAND in figures 1 and 3 looks different from what is sketched out in figure 2. But let’s look more closely.

The three main architectural differences are:

1. Wider wordlines encompassing pairs of channel holes instead of narrow wordlines with single lines of channel holes.
2.  Staggered pairs of channel holes placed along length of wordlines.
3.  Slits between wordlines filled with a conductor instead of a dielectric.

Remember though, that there is still risk in assuming that Figure 3 is totally accurate based on Figure 1. The probability of accuracy is high, but best to wait for the more detailed analysis from Chipworks to make sure. Nevertheless, assuming Figure 3 is accurate, why would Samsung make such changes from what they have published in the academic literature that was used to generate figure 2?

First of all, changes from device-based academic papers to what eventually appears in a product are not strange since product-level optimization usually demands this. My guesses for these changes are the following:

1. Wider wordlines allow lower resistance in each wordline which may be important for read and program speeds. Such a wide wordline also allows placing more channels side by side (two in this case) in a line between slits. Doing this means that the relatively wide slit size is divided among more cells and has less of an impact on cell size compared to the case shown in Figure 2. The encouragement to do this may have been overwhelming given the wide-looking slit in Figure 1 (now filled with tungsten).
2. Staggering the pairs of channel holes allows a slight reduction in cell size in the direction of the wordline and so counteracts other effects that may increase cell size such as wider slits that need to be filled with conducting material.
3. Slits filled with conductor, probably tungsten, allow metal strapping and therefore lower resistance of the N+ doped NAND string sources in the bulk of the silicon. Again, this may have been absolutely necessary to avoid voltage drops along otherwise high resistance source lines during read, program and erase. Figure 1 may actually show the metal filled slits punching through the N+ doped sources and connecting to a p-doped well underneath although we can’t be certain. If it does, it would short the sources to their wells which has been done before by Samsung in their more conventional thin-film transistor version of their TANOS NAND about eight years ago.

In summary, Samsung’s product 86 Gbit 32-layer 2^nd generation V-NAND looks similar to what has been guessed at but with interesting adjustments. The question though is what is the cell size since this is the major factor for cost per bit? Figure 4 shows a red rectangle marking out the area of two cells. The cell size would be half this area. Note that the slit width is therefore divided by two as its contribution to cell area.

Since Chipworks did not provide dimensions in their cross section, it is difficult to know what the cell pitches are in Figure 4. However, what can be said with some certainty is that the effective cell area will be about 150nm by 260nm since these numbers “fit in” with the “top down” calculations based on die size, array efficiencies, numbers of layers and capacities as given in figure 2.

It appears therefore that the product level optimizations that Samsung have had to go through in their 86 Gbit 32-layer 2^nd generation V-NAND have not resulted in a smaller cell than their ~ 25F² number where F is held at 40nm.

Let me say first of all, hearty congratulations to Samsung on an amazing engineering feat in making a real product out of their vertical channel V-NAND technology.

Now that that is out of the way, we need to consider the following. We have had to wait almost exactly a year from Samsung’s Flash Memory Summit 2013 announcement of V-NAND in mass production to actually (almost) figuring out  cell size and structure. This contrasts with the usual approach where stand-alone Flash cell size in a new technology is displayed with pride by its inventor at any one of the major technical conferences.

In addition, the market chosen by Samsung (least cost sensitive) tells me that the original motivation of lowering bit cost presented in their original technical paper in 2009 (where this approach was called “TCAT”) seems to have faded away from view.

So, do I descry the “Spires of El Dorado”? Yes, but they are shorter than we initially thought and, to me at least, look like gold plate rather than solid gold. ~ AJW