Somehow in all my preparations for the 2014 3D InCites Awards and planning the schedule for SEMICON West this week, a significant piece of news slipped right by usually alert 3D radar for TWO WHOLE DAYS! On Tuesday, Micron issued a press release announcing a collaboration with Intel to deliver an on-package 3D memory solution for Intel’s next-generation Xeon Phi™ processor, codenamed “Knights Landing.” The statement goes on to say that the companies have been working on this for some time to solve memory wall issues, and that it leverages the same fundamental DRAM and stacking technologies found in Micron’s HMC.
What differentiates HMC from this so-called High Performance On-Package Memory? While I was unable to reach a Micron representative on such short notice, I did find a list of FAQs published on the Micron Website that addresses some of my questions regarding this question. (A coincidence? I think not). According to Micron, while this memory solution leverages the same technology as HMC, it was optimized specifically for integration in Intel’s Knight’s Landing platform. There are no plans for standardization, and it is not available to other customers. On the other hand, the HMC is the outcome of the HMC Consortium (HMCC), which is “devoted to driving open-standard and interface and protocol platforms”. Members of the HMCC include developer members, Altera, ARM, IBM, Micron, Open-Silicon, Sansung, and SK Hynix, and Xilinx; as well as a host of adopter members.
Another significant advancement for “Knight’s Landing” is that it will feature a new interconnect fabric Intel has called “Omni Scale” that will be integrated onto the chip. According to this post by Daniel Robinson on V3.co.uk, the Omni Scale uses Intel’s Silicon Photonics fibre-optic technology. (This story just keeps getting better.)
According to Micron, the target application for the “Knight’s Landing” project is not consumer mobile electronics, but high-performance computing systems – which is in line with industry predictions that 3D technologies will first be implemented in high performance systems that will bear cost of integrating 3D memory to gain performance benefits. A statement issued April 29 by U.S. Department of Energy’s (DOE) National Energy Research Scientific Computing (NERSC) Center announced that NERSC has contracted Intel and super-computer manufacturer Cray Inc., to build “the next-generation super computer to enable scientific discovery at the DOE’s Office of Science (DOE SC).”
This announcement describes “Knight’s Landing” as “a self-hosted, manycore processor with on-package high bandwidth memory (HBM) that delivers more than 3 teraFLOPS of double-precision peak performance per single socket node.” There is no mention of Micron in this earlier press release, but the reference to HBM is also inline with HMC’s 3D memory stacking technologies. Cray’s new system is scheduled for delivery sometime in 2016, and will reportedly deliver “10x the sustained computing capability of NERSC’s Hopper system, a Cray XE6 supercomputer.
Little fun fact: NRSC has a tradition of naming its computers after noted scientists. They will name this next-generation supercomputer “Cori”, in honor of biochemist and Nobel Laureate Gerty Cori, the first American woman to receive a Nobel Prize in science. Go SemiSisters!
I think this is pretty significant news for the 3D world. I can’t believe I didn’t see this until today. I swear, I just looked away for a MINUTE! Hope to find out more at SEMICON West. ~ F.v.T.
Disclaimer: No where in the press releases do they refer to the on-package memory solution as 3D memory. I made the assumption based on the fact that its leveraging fundamental DRAM and stacking technologies as HMC.
