At the beginning of April, the Semiconductor Industry Association released the 2013 International Roadmap for Semiconductors (ITRS), which has traditionally served as a guide for “assessing and improving the future of semiconductor technology,” according to Brian Toohey, president and CEO, Semiconductor Industry Association.
Sponsored by five regions of the world including Europe, Japan, Korea, Taiwan and the United States, the goal of the ITRS committee is to identify gaps, technical needs and potential solutions related to semiconductor technology. According to the press release issued by the SIA, among the findings and predictions of the 2013 ITRS roadmap with regards to devices is that “the combination of 3D device architecture and low power devices will usher in a new era of scaling identified in short as ‘3D Power Scaling.’ The increase in the number of transistors per unit area will eventually be accomplished by stacking multiple layers of transistors.“ Which goes hand-in-hand with that the roadmap predicts for the future of systems integration, stating ”the integration of multiple technologies in a limited space (e.g., GPS, phone, tablet, mobile phones, etc.) has revolutionized the semiconductor industry by shifting the main goal of any design from a performance driven approach to a reduced power driven approach.” In other words, all roads point to reduced power as the most pressing need, and 3D SoC (aka 3D power scaling) will be the way to do it, whether they are 3D transistors, Monolithic 3D IC, or 3D stacked IC.
A recent post in Advanced Substrate News co-authored by Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti, titled Going Up! Monolithic 3D as an Alternative to CMOS Scaling, supports this theory, and compares current approaches to 3D IC stacking using TSVs to interconnect stacked die, with the advantages of Monolithic 3D (M3D) – also known as sequential 3D.
According the post, M3D increases density “sequentially” within a single process flow, as opposed to the TSV approach, which is applied to die that have already been processed. One of the benefits noted is that M3D allows for increasing density without requiring downscaling of individual features. M3D could also provide a gain in performance by reducing the metal wiring delay, thanks to direct contact between transistor levels. From a cost perspective, M3D appears to offer a competitive advantage over equivalent N+1 scaling nodes: the scaling achieved in node N and even N-1 can be leveraged for another generation. The post also demonstrates the M3D process flow, based on SOI wafers.
Leti is so sure about the promise this technology holds, that it has begun building an M3D ecosystem of partners to “enable rapid industrialization of the process.” QUALCOMM has already thrown its hat in the ring, having recently partnered with LETI on the M3D mission and dedicating resources to assess the feasibility of M3D.
In other 2.5D and 3D coverage, SemiEngineering’s Mark LePedus canvased the main players in the industry to get a better idea of the current direction of 2.5D and 3D IC progress. His post is titled Time To Revisit 2.5D and 3D, which I find to be amusing as most of us never stepped away from 2.5D and 3D, but have had our eye firmly on the prize the whole time. Nethertheless, LePedus gives a comprehensive update on the 3D roadmap, the various approaches to collaboration, expected product ramps from major players, and has some straight numbers on how much 3D is going to cost us, and a breakdown of cost by process.
Overall, the post doesn’t reveal anything earth shattering, and it comes to the same conclusion that we’ve been talking about on 3D InCites for some time; a gradual ramp, with costs coming down gradually to make sense for the next round of products. ~ F.v.T.
