Every once in a while, it’s important to remember that through silicon vias (TSVs) might not be the only game in town. While many continue to forge ahead, with commercialization so close we can taste it, others are already moving on to the next thing or looking for alternatives. Will these beat TSVs to the finish line? Not likely, considering this industry’s slow-to-adopt culture. But it’s still exciting to see what’s in the R&D pipeline. I came across a couple posts today that showcase other ways to get your 3D IC on. One was completely new to me, and involves a through chip interface (TCI) that interconnects stacked chips wirelessly. This work is being spearheaded by a start-up, Thru Chip Communications. The other is not about a new concept, but is about developments in monolithic 3D ICs and progress being made by researchers at CEA Leti.
In a Feb 21, 2014 post on EE Times titled, Startup Stacks Chips Wirelessly, Rick Merritt reports on inroads Thru Chip Communications is making with a technology based on an inductive coupling link that the company claims can interconnect chips wirelessly, and could potentially “save 40% of the costs of TSVs now in development.” The approach also reportedly is simpler and uses less power. Target applications for this technology is DRAM and Flash memory.
Merritt quotes Herb Reiter, principal of EDA2ASIC Consulting in Los Gatos, Calif. (and 3D InCites technical advisory board member), who expressed skepticism. “The wireless approach eliminates difficult steps needed for TSVs, such as extreme thinning of wafers, however it opens up new issues about aligning coils and eliminating interference between them,” he said. Reiter goes on to express concern that the coils could not be made small enough to compete in die area with TSV even including the TSV keep-out-zone. Check out the original post for details and a detailed slide show of how it all works. I’d be interested in what readers think about this technology’s potential.
We’ve been following the progress of monolithic 3D processes over the past couple of years. Monolithic 3D ICs do not rely on stacking chips with TSVs, but rather use traditional front-end processes to essentially build-as-you go; creating layers of circuitry in a sequential process on top of existing transistor layers. In theory, this elegant concept seems simple, but in practice, has proven to be more complicated because the temperatures required to build additional layers compromise the circuitry underneath. However, according to a recent post on IEEE Spectrum, researchers at CEA Leti are making progress in developing low-temperature processes. The Grenoble-based research institute has “developed one scheme that bonds a second silicon wafer on top of the first tier of circuitry. All but a thin silicon layer on this second wafer is stripped away. A second layer of transistors is built using a process called solid-phase epitaxy, in which a mixture of dopant atoms and amorphous silicon is laid down. The mix is then heated to just 600 °C, giving the silicon enough energy to crystallize. As a last step, connections are made by etching holes down to the first layer and filling them with copper,” writes Rachel Courtland, IEEE Spectrum, in The Rise of the Monolithic 3D Chip” http://spectrum.ieee.org/semiconductors/design/the-rise-of-the-monolithic-3d-chip
Courtland also reports that Leti and Qualcomm have entered into an agreement to test this process for mass production. She also cites a few other groups working on monolithic 3D process. I recommend reading the full post for a detailed explanation of what monolithic 3D is and where it’s going. ~ F.v.T.
