Nothing says “Christmas is coming” to me like the annual 3D ASIP Conference that has taken place each December for the past 10 years. I actually got a late start, attending my first 3D ASIP in 2009 after I launched 3D InCites, but since then I have attended every one. I’m pretty sure I missed at least one Christmas school performance because of it. That’s how dedicated I am to it; it’s that good. In honor of its 10th Anniversary, I thought it might be fun to revisit some of the highlights of past conferences, and also give you my observations about this year’s agenda.
In 2009, the EDA tool guys were taking it on the chin for not having developed any solutions, but were getting a little tired of all the finger pointing, and came to their own defense and spoke out about their progress.
2009 was the year for start-ups, with NEXX systems announcing its 100th tool install; Tezzaron had reported a 500% increase in revenue and a successful multi-project wafer program. This was the year Tezzaron developed it’s FaStack process and built-in self test and repair (BISTAR), and formed and alliance with SVTC in Austin. Ziptronix licensed its DBI technology to Raytheon Vision Systems, and ALLVIA prepared for volume production of TSV wafers by purchasing a fab in Hillsborough, Oregon.
In 2010, spirits were up because Samsung had just announced development of its 8GB dual inline memory module using 3D TSVs; IBM and SEMTECH announced they would develop a high-performance integrated ADC/DSP platform using IBM’s silicon interposer and Cu TSVs, and the biggest news of all – Xilinx announced its silicon stacking technology was headed for production and would ramp in 2011/2012. By 2010, the EDA vendors were mostly engaged (Synopsys thought leveraging existing tools was good enough – no need to build 3D tools from the ground up), the test community was involved, and better need for standards was defined. More people were starting to believe that TSVs would become industrialized.
By 2011, everyone from Ivo Bolson of Xilinx to Doug Yu of TSMC was declaring, “3D ICs are here”, despite concerns about keep-out-zones, thermal management, and design methodologies. That was the year TSMC declared it was ready to provide end-to-end processes for 3D TSVs. Three supply chain options were identified: turnkey, middle-end-of-line (MEOL) at the foundry, and MEOL at the OSAT. Thin wafer handling was a key challenge.
3DASIP 2012 saw a brief change in venue to Redwood City (back in Burlingame this year). Xilinx’ Liam Madden presented his “Stackonomics” theory, arguing the cost issue by saying scaling no longer makes economic sense, and we need to focus on total system cost when evaluating the benefits of moving to TSVs. Dave McCann of GLOBALFOUNDRIES talked about the company’s collaborative supply chain model, inroads in test were reported, remaining challenges in temporary bond/debond were featured. In 2012, Tezzaron exhibited with its recently acquired subsidiary, Novati (formerly SVTC Austin), and Ziptronix announced its license agreement with Tezzaron and shortly thereafter, Novati, for its ZiBond and DBI technologies.
So what does 3D ASIP 2013 have in store for its attendees? Will we see the age-old challenges of thin wafer handling, thermal management, and cost of ownership addressed? Absolutely, and I will diligently report on these. But what I’m most excited about are the pre-conference symposium presentations on Si Photonics, which will be by 3D IC technology.
As most of the events I attend have reports on market progress for 2.5D and 3D ICs, I’m curious if there is new information (since, say IWLPC). What I am happy to see is representation from more than just one market research firm during the session, “3D ICs: Are We Making Progress?” That should make for some opposing viewpoints, which is always fun to write about.
I’m also looking forward to Doug Yu’s keynote, as he’s been the voice of TSMC over the years at 3D ASIP, and it will be interesting to hear the company’s most latest position, as they’ve gone from promoting end-to-end services to being open to collaboration for high volume manufacturing. Plus, the title of his talk, Déjà Vu – Wafer Level System Integration Technology makes me think he’s been here before.
One clearly notable change I’ve noticed in this year’s agenda is less speaker representation from the supplier side and even R&D, and more from manufacturing and design houses. That should make for new things to write about! No question – I’m looking forward to another great 3D ASIP. Hope to see you there. ~F.v.T.
