I took a detour to work on Friday (Oct 18, 2013), stopping in at Freescale Semiconductor (Tempe AZ) to attend the Arizona SEMI Breakfast Forum. The topic was right up my alley: (which is why I went, of course!) “New Advanced Packaging Insights on Technology and Applications“. Featured speakers included Garrett Oakes, EV Group, who focused on copper (Cu) pillars from “lab to fab”; Semico Research’s Jim Feldhan, who delivered a market trends forecast; Amkor’s Ron Huemoeller, who talked about the migration of advanced packaging technologies from substrate integration to modularity; ASE’s John Hunt, who focused on the evolution of wafer level packaging; and wrapping up with Scott Hayes, of Freescale Semiconductor, who talked about system-in-package (SiP) solutions for heterogeneous integration. As I expected, 3D packaging (2.5D and 3D IC) was pervasive throughout all the talks and appears on everyone’s roadmaps.
Roadmap to fine-pitch bumps
After giving a high-level view 2.5D and 3D IC progress this far, including some exciting statistics demonstrating the shift in CMOS image sensor market share from front side illuminated sensors to backside illuminated (BSI) sensors, Oakes talked about the advantages of Cu pillars over traditional solder bumps, like the elimination of solder bump collapse during reflow; the ability to achieve higher interconnect densities, and more uniform bump pitch and standoff heights that lead to more complete underfill; all of which make Cu pillars a structural component of the bond.
Oakes also outlined developments in solid-liquid inter-diffusion (SLID) soldering, and indium/solder lift-off bumping. Both are transient liquid phase (TLP) processes. SLID allows for the creation of intermetallic compounds within the pad metal, and is preferred in chip stacking because of the high thermal budget. Indium/solder lift-off can achieve finer pitch bumps than SLID and tin-silver (SnAg) capped Cu pillars. It is furthest out on the roadmap to finer pitch bumps.
Mobility Rules
Good news from Jim Feldhan – overall the semiconductor market growth will reach 6% this year and 10% next year. Even better news, by 2017, the mobile device market will be almost 5 times as large as the traditional desktop and notebook markets. The expectation will be that we “hold the same processing power in our hand as in our desktop or notebook,” noted Feldhan. He shared this little fun factoid: It took 26 years for PCs to reach a billion units sold, yet feature phones reached that number 2.8 times faster, and smartphones reached it 2.3 times faster. We can expect 1.3B smartphone units will be in the market by 2017.
And that’s just the beginning. Both Feldhan and Hayes talked about the Internet of Things and the impact it will have on the future of semiconductor systems integration. Feldhan noted that the IoT is “more than just WiFi” and requires the cloud, the communications infrastructure and mobile devices. Based on just the residential portion (20%) of the total expected IoT market in the next 10 years, research indicates that there are 70 appliances within the average home that could become IoT connected – or 18B appliances total. As a result, we could be looking at 160B new semiconductor devices sold annually by 2023. Pretty much boggles the mind, doesn’t it?
Hayes shared a picture of the IoT painted by Peter Hartwell, senior researcher, HP Labs, in this quote: “Within a trillion sensors embedded in the environment – all connected by computing systems, software and services – it will be possible to hear the heartbeat of the earth, impacting human interaction with the globe as profoundly as the internet has revolutionized communications.”
Calling the IoT “the network of all networks connected through the largest control data network in the word,” Hayes said it’s all about the services. Sensing, processing and connectivity forms the basis of the IoT. This situation calls for miniaturization and advances in packaging technologies to create system in packaging (SiP) solutions. Freescale is playing an active role in this; particularly with it’s redistributed chip packaging technology (RCP). RCP is Freescale’s version of fan-out wafer level packaging (FOWLP). Hayes showed examples of the technology’s evolution, and its potential all the way to a 3D wafer level package-on-package (PoP) configuration, he called RCP 3D Stacked SiP module. One of Freescale’s secret to short time-to-market (2-5 months for testable samples, claims Hayes) is to procure components that are available in the market and integrating them into a heterogeneous SiP.
The end of Planar Scaling
Calling 3D packaging the “integration tool kit” that facilitates the migration to modularity, Ron Huemoeller focused his talk on such enabling technologies as embedded die, deconstruction and departitioning of die, advanced substrates, and interposer solutions. Reaching the “end of planar scaling” and moving into FinFETs requires higher levels of integration at the packaging level. “We can’t lose focus on thinness, and without compromising on cost,” he cautioned.
“3D packaging is absolutely necessary. Embedding die is one way to get that done,” said Huemoeller. While most of us think only of stacking die to achieve 3D packages, we were reminded that 3D comprises all levels of integration, including embedded die. Embedded passives are already in high volume manufacturing (HVM), and active die are in low-level manufacturing and gaining interest. Progress with thinner substrates with increased I/O capabilities, improved materials, and better electrical performance is also key.
On the topic of departitioning/deconstructing die – Huemoeller explained that its been discovered that GPUs and CPUs perform better if they are separate than on the same die. As it turns out, deconstruction lowers power usage and increase performance.
As we know, the role of interposers is significant in this space. Huemoeller talked about silicon, glass and organic interposers, and where they fit into the scheme of things. He said silicon will dominate the high-end computing markets, such as Xilinx FPGA 2.5D product, and play a prominent role in the mid-end, which includes GPUs, CPUs, and high-end memory. If and when the glass interposer infrastructure is developed, he targeted mid-end computing markets for that. Organic may also play a role in mid end, but will likely be most prominent in the low-end mobile computing market because it has a large infrastructure to leverage, noted Huemoeller. He also stressed the need for a silicon interposer supply that is not bundled with logic, and says there is growth opportunity in that space.
The evolution of WLCSP
While John Hunt just briefly touched on ASE’s 3D wafer level packaging (WLP) activities at the end of his talk, he offered some interesting takeaways and stats on the wafer level chip scale package (WLCSP) market and its increasingly important role in mobile applications. The biggest growth market for WLCSP is portable consumer devices (smartphones and tablets), and will make up 80% of phones by 2017. Hunt said that a poll conducted by ASE of their WLP customers showed that thin is the primary driver for WLCSP, followed by large die, High I/O, cost reduction, MEMS, wafer fan-out, (PoP and SiP applications), new solder alloys and high power.
While 3D TSV for 200mm and 300mm is available at ASE, and the company has demonstrated die-on-die capabilities, their key offerings in 3D WLP is a double-sided 3D FOWLP PoP and a double-sided 3D FOWLP module assembly.
One thing John Hunt said that struck a chord was in reference to how OSAT functions have changed over time. 13 years ago, advanced packaging was all about mechanical operations like die placement and wire-bond, he noted. Now they have the capacity to do front-end processes like metallization, wafer bumping, thin wafer handling, and backside processing for 2.5D and 3D stacking. It seems to me that clearly, the role of the OSAT has changed, and with it, the value proposition. ~ F.v.T.
