Big news for 3D ICs this week as TSMC and its OIP Ecosystem Partners announce the release of silicon-validated reference flows for both 3D IC stacks and 16nm FinFETS (everyone else puts the 16nm FinFETS first, but I’m most excited about the 3D IC news.)

According to Peter Clarke in EETimes, “silicon validation of these flows signifies the opening up of the manufacturing processes for the design of production volume chips.” Here’s the important part to know about the 3D IC reference flows: validation is for the design of vertically stacked structures and multi-die assemblies. According to a TSMC press release, “the 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC’s 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; and TSV-to-TSV coupling extraction. You can read Clarke’s analysis of all three reference flows here.

SemiWiki’s Paul McLellen gives an expanded explanation of the 3D IC flow, which he says is still a work in progress and not in its final stage. Still, it’s a positive sign. He also explains that TSMC’s TTS is a true 3D device, because it does not rely on an interposer, but uses TSVs to stack memory on top of a 28nm logic die, as well as through to the backside RDL of the logic die to C4 bumps. (It sounds very similar to Micron’s Hybrid Memory Cube, now that I think about it.)

Speaking of the HMC, earlier this month, Altera and Micron announced they had jointly demonstrated successful interoperability between Altera Stratix® V FPGAs and Micron’s Hybrid Memory Cube, which reportedly enables system designers to evaluate the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing design. While this is exciting news for most of us who have been waiting for signs of progress, EDN’s Loring Wirbel, questions whether 3D packaging will limit HMC’s popularity when compared with what he calls “special purpose non-volatiles”.  Here again I think is a comparison of apples to oranges, and so I find Wirbel’s argument a bit arbitrary. HMC is not an alternative to DRAM as he suggests. It is stacked DRAM on a logic layer, all connected by through silicon vias (TSVs). Further, the applications for volatile memory like DRAM differ widely from those of non-volatile memory (like 3DNAND). In my opinion, comparing this clear leap forward for the HMC with the uncertain progress of non-volatile memories has little, if any basis.

However, if you are looking for a technically accurate analysis of the Altera/Micron announcement, I recommend Max Maxfield’s blog post, Altera’s FPGA’s meet Micron’s Hybrid Memory Cubes. Even though Max claims to not be an expert on memory archtectures, he does a fine job explaining how HMC solves the controller overhead issue by bringing all the complicated controlling inside the HMC. Maxfield seemed pretty confident that when HMC goes into volume production in early 2014, Altera will be ready and waiting to implement it to the Stratix V FPGA. Now there’s an attitude I can agree with.  ~ F.v.T.