This is part of a series of short interviews, based on face-to-face meetings at SEMICON West 2013.
For a long time, the jury was out on the probe-ability of micro-bumped TSV wafers. The jury was also unsure whether or not there was any point to probing to ensure known good die (KGD) or will “probably good die” suffice, given the cost of test?
Probe test companies, FormFactor and Microprobe were each working on TSV probe solutions independently. The companies recently merged, and have ramped up combined efforts, working with customers on wafer test strategy for 3D ICs. I met with Mike Slessor, Ph.D, Sr. VP and general manager, Microprobe Product Business Unit, Formfactor, to learn more about where they are taking these efforts.
Slessor explained that FormFactor’s 3D probe strategy is to probe 3D packaging interfaces including the vias, micro-bumps and interposers. Microbump probing is confined to early development prior to high volume manufacturing (HVM). Another part of a good probe strategy is to probe dummy sacrificial pads.
Why not wait and just test the stacked devices? It depends on the relative value of the different components, explained Slessor. “A $1 DRAM better not take down a $25 applications processor,” he said. Supplying known-good processors require an expensive test suite. When is it worth it? When the incremental cost of test is less than the cost of tossing the part.
“We do wafer test because we don’t want to package bad parts. The key is to test high probability defect modes,” said Slessor. “Customers always evolve test strategies to remove test that doesn’t expose defects. You start with exhaustive test sets, and then reduce as you go. You reduce the cost of test by getting rid of those tests that aren’t turning up defects or those that have few defects. The rationale is around the cost.”
Formfactor’s first product for testing micro-bumped TSVs is its NanoPierce contactor; a socket solution for direct testing of TSVs and micro-bump arrays for 3D IC integration. NanoPierce contactors gently pierce the microbump without damaging the structure. The product was nominated for a 2013 3D InCites Award. Mainstream wafer test today with “standard” probe cards is in the 100-150µm pitch range, explained Slessor, whereas NanoPierce (which is targeted at the 50µm JEDEC standard) is a significant shrink from today’s mainstream. The company is spearheading pathfinding R&D efforts to set a pitch reduction roadmap, and is working with partners on test die before packaging them into a 3D structure.
Slessor predicts that for HVM, the industry will use dummy pads to characterize the devices early on through the microbumps. The solution will be a precise and reliable set of contactors that exhibit good yield and long lifetime. “The details are different, but the industry has done this before.” He noted. “We’re looking at the usual drivers and are increasing parallelism to drive down the cost of test.” ~ F.v.T.
