For me, SEMICON West involves a careful balance of attending sessions, keynotes and panels, combined with one-on-one interviews with thought leaders in 3D ICs, as well as manufacturing suppliers who have the onerous task of developing, promoting, and selling the next great solution for 2.5D and 3D IC manufacturing. Over the course of the 3 days, things I hear percolate in my head, and form questions that I might pose to my next unsuspecting victim.
Imec’s Ludo Deferm is a thought leader who is willing to answer my questions, even if they are outside the planned interview scope. This year my discussion with him immediately followed the R&D panel, from which I emerged slightly frustrated by Michael Liehr’s comment that 3D ICs won’t take of until the costs of 3D ICs are closer to typical packaging costs. (Note to reader: this might be a recurring theme in ensuing posts from SEMICON West, because while it is true, I think this mindset is one that has to change.)
Deferm’s take on the topic: when it comes down to the packaging processes, the OSATS traditionally feel the price pressure. “You’re not going to change the OSAT mindset,” he explained. “The customer has to want a high-level system and provide additional money for the packaging.” Ok, I’ll buy that. He said it falls to the system engineer. We need to provide design kits that match the foundries’ and addresses the higher level of interconnect. Instead of adding a layer, we add a platform. EDA vendors can implement it in the floorplan, and we have a system for two providers, the OSAT and the foundry. Alternatively, we need a design kit targeted to the packaging environment; we need people with experience in process technology, interconnect technology and packaging technology to come together and produce a PDK (where have I heard this before? Oh yes, Interconnectology!) In this case, the “P” stands for “packaging.” If there are two providers (foundry and OSAT) then the kit is defined by who is going to manufacture it.
Moving on to imec’s 3D IC news – Dow Corning has joined imec’s 3D program to test and implement its temporary debonding solution in imec’s process flow. Dow Corning recently introduced its room temperature, low force bond material to the industry, offering yet another alternative for debonding. With so many solutions already qualified by imec — for example, imec is already partners with Brewer Science for a number of material solutions for temporary bond/debond including ZoneBond and thermal slide debonding — I asked Deferm why imec would have interest in this latest solution.
Deferm explained that while existing technologies work fine for interposers and coarser TSV applications, as the industry moves to higher aspect ratio vias, and more vias in order to reduce cost, TSV device wafers are even more delicate.
“A full 300mm wafer with lots of TSVs creates a weaker substrate that’s hard to debond without creating stress,” explained Deferm. “Thermal treatment creates stress. It’s a yield killer for 3D. We need alternatives where we can do room temperature bonding.”
While ZoneBond works, Deferm says it’s important to explore more methodologies as the 3D IC TSV process flow becomes more complex. What’s needed is a simple process that won’t destroy the yield, and has sufficient strength at the bonding level without causing thermal and mechanical stress. What’s compelling about the Dow Corning solution, he said, is that it’s a two-layer release. “The bond breaks where it should, without causing mechanical stress,” he explained.
So while the industry works out the supply chain kinks to bring 3D ICs to commercialization, imec is moving on to the next phase of development, working to optimize processes that will lower cost and also increase density for high performance needs that are immanent. ~ F.v.T.
