While there is still a lot to report about the European TSV Summit, I wanted to catch everyone up on some recent developments at companies that have come my way via press release; beginning with the most recent:
STATS ChipPAC and UMC announced that they have demonstrated the world’s first TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The companies report that the 3D IC chip stack, a wide I/O memory test chip stacked on TSV-embedded 28nm processor test chip, successfully reached a milestone in package-level reliability assessment, thereby proving out the collaboration between UMC and STATS. According to the companies, UMC provides the front-end-of-line (FEOL) processes in its foundry, while STATS performs middle-end-of-line (MEOL) and back-end-of-line (BEOL) processes.
Prior to and during the TSV Summit, imec announced two technology developments in the 3D IC space, in conjunction with its partners, PVA Tepla and Cadence, respectively.
The big news with PVA Tepla involved breakthrough results with detecting TSV voids at wafer-level after TSV copper plating using scanning electron microscopy. Initially, the collaboration was established to develop a process for detecting voids after temporary wafer bonding. Upon achieving that, imec used PVA Tepla’s high-resolution capability GHz frequency SAM tool to successfully detect voids in TSVs of 5µm diameter and 50µm depth, immediately after plating.
On the 3D IC design side, imec announced that together with Cadence Design Systems they have developed, implemented and validated an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. The automated design for test solution has been validated on an interposer-based 3D stacked IC comprising a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The DfT solution includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAMs) of the 3D test architecture. ~ F.v.T.
