Given the building momentum around 3D integration schemes and the attention it’s getting as the semiconductor bright spot, it’s no surprise that at this year’s SEMICON West, there are more programs focused on 3D integration technology issues, both on and off-site, than last year. In fact, if you want to plan your itinerary around all things 3D, you can easily fill your schedule.(Trust me on this one, my dance card is overflowing.)
Whet your appetite by joining in the discussion online at the aptly-named, Brightspots 3D IC Forum. Moderated by yours truly, this roundtable discussion will address critical issues surrounding 3D integration from the front-end through the back-end. Discussion opens at 6am PT, on July 6 (looks like I’ll be moderating this one in my jammies) and closes July 24. The more people who participate, the more interesting I’m sure it will be, so sign up early and visit often.
SEMI has organized several program events around 3D integration beginning with a Packaging Summit on Tuesday, July 14 from 3:30-5:30, that begs the question: When the Package is the Product, will 3D Integration be the Holy Grail? This summit will address the business side of 3D, discussing how these emerging technologies will overcome cost and time-to-market to find their way into consumer electronic applications. Additionally, Wed. July 15 from 2-4pm, the Test, Assembly and Packaging TechXPOT will feature a technical session, The 3D TSV Revolution, It’s More Than Just Stacking! with speakers addressing 3D integration technologies such as systems integration, system design, TSV processes, materials issues, thin wafer handling and chip stacking, as well as the OSAT perspective.
Then, the Thursday session from 11:00 – 1:20 looks at Survivability Through Collaboration, examining the effectiveness of collaboration between the R&D and manufacturing communities in bring 3D schemes to fruition. Additionally, one presentation (from 2:50-3:10 pm) during the test strategies session on Tuesday talks about Semiconductor Test in the Third Dimension. As test is one of the missing links in the 3D supply chain, it would be great to find some insight here.
Off-site, SUSS MicroTec has just announced they will be hosting a free workshop at the St. Regis, Wed. July 15 from 2-5pm on the topic of Thin Wafer Processing for 3D TSV Applications, in which materials and equipment manufacturers will reveal the latest innovations in thin wafer support systems & backside processing. Also on Wednesday from 1pm-6pm, SEMATECH will be hosting a 3D Metrology Workshop. Attendees should hope to gain information on how new and existing wafer metrology technologies can adapted to measure and improve 3D interconnect processes.
It’s pretty clear I’m going to have to clone myself, at least on Wednesday, to fit all this in! Hope to bump into you there. – F.v.T.
