It’s been a whirlwind of conferences these past few weeks, and as a result, I have attended FOUR panel discussions on 2.5D and 3D related topics. (I already wrote about the 3D Test Workshop Panel – 3D Buzz Hype or Reality. It’s stirred quite a discussion.) The day before I moderated that, I attended IWLPC’s 3D Panel: How did We Get Here? Where Do We Need to Go Now? featuring the updates of 6 industry experts from across the supply chain: Jeff Calvert, Ph.D,, Dow Chemical; John Lau, Ph.D. ITRI; David Love, Genapsys, Inc.; Garrett Oakes, EV Group; Peter Ramm, Ph.D, Fraunhofer EMFT; and Tom Strothmann, STATS ChipPAC. To get things rolling, Moderator Keith Cooper, SET-NA, posed two questions: What are the most significant events in 3D packaging? And where do we go from here? Here’s what they had to say (in no particular order):
Love gave the shortest presentation but made the biggest point, in my opinion. (I also had the opportunity to hear it a second time on the panel for Roadmaps for Multidie Integration Symposium on Thursday, so it’s also the freshest in my mind.)
His key message was this: Horizontal Multi-chip Modules (MCMs), 2D and 2.5D technologies may solve local routing issues, thereby solving that bandwidth bottleneck at low power. Unfortunately, he said this is only useful for Memory and FPGAs. “All other chips have global routing that need high speed,” he explains. “For chips with high global routing that aren’t Memory or FPGAs, 2D or 2.5D helps very little.” For devices with high global routing, he says the highest bandwidth solution is 3D, with optimized layout of each layer. This is why we need to work out the remaining challenges; because we need 3D.
Strothmann showed the evolution of 3D packages, going all the way back to wirebond stacked die, through package-on-package (PoP) into current developments like Wide I/O stacking memory on processor to drive home the message that applications require more complex and customized packaging solutions, which requires collaborations for the 3D ecosystem between foundries and OSATs to create a durable supply chain. STAT’s strategy, he said, is not to provide vias, but to pick up the process at the middle-end-of-line (MEOL). He also stressed the capex required for OSATS to do MEOL processes is pretty significant.
Reporting from the materials perspective, Calvert said Dow’s approach was to optimize existing materials developed for the advanced packaging market for 2.5D and 3D packaging. For example, the company has been working on its Cu TSV fill material to improve its performance for filling TSVs with smaller feature sizes and higher aspect ratios. Calvert talked about needs and gaps, and how the point is not that there’s a 2-year offset in terms of forecasted ramp for 3D, but that the onset of interposer technology, while contributing to production in the near-term, has moved out the necessity of 3D technology.
Good news from the world of temporary bond/debond (TB/DB) Oakes says TB/DB system designs have matured and stabilized in the past two years, and that there are now multiple suppliers for both the hardware (equipment) and software (materials). Additionally, the carrier wafer “universe” has narrowed to standard silicon or glass that matches the process wafer. Edge trimming to protect the process wafer is common practice. Needs and gaps to be addressed from the process perspective include a lower cost of ownership, and handling high stressed wafer during the debonding sequence to keep them flat and get them to the next process.
Both Ramm and Lau offered the R&D perspective. After citing the usual remaining issues and successes, Ramm declared that 3D technology is now entering mainstream with promising future applications for heterogeneous technologies. He said the choice of 3D process used depends on the performance that you really need and the reliability requirements of the target application. ( Incidentally, SemiMD’s Mark LePedus interviewed Peter Ramm about one of the European projects he oversees eBRAIN.)
Lau’s message was directed at the supply chain models. He ran through all the process flows and offered opinions of what process should be handled by whom, and which should be avoided altogether.
- MEOL should be handled at the OSAT, and moreover it should be more than enough to keep them busy. “They need to make themselves ready for a robust and high yield manufacturing process for MEOL,” he said.
- Via last should be avoided because of logistics
- Via mid is the way to go and should be performed by the Fab
- With passive interposer, the Fab vs. OSAT decision depends on line width and spacing.
Once again, in this particular forum, test continues to be elusive. Discussion flipped back and forth between the cost of test, developing an optimized test strategy and deploying it, the need for a test architecture to ensure good parts, and device level test vs. system level test. Luckily I heard more specific information about this at MEPTEC’s Known Good Die Symposium – but that’s another story for another day.
So if the stars are aligning, and the need is there, what’s the hold up? It all boils down to simple economics “If there are any alternatives to do lower cost process to achieve the same functionality and performance, that’s what is done. There’s always a cheaper way, that’s why it (3D) slips.” noted Strothman.
I think it was Love who pointed out that the discussion over the past six months has changed from “playing” to wondering about the schedule. Behind the scenes, work is being done on real parts. It’s clear that there’s a brick wall between signal propagation delay that can’t be solved any other way than 3D, and that when it happens, we’ll see a broad release of 3D devices. ~ F.v.T
