It’s been one of those Mondays. I started making the coffee this morning (put in a clean filter, poured in the water) before I got sidetracked and hit the shower without ever putting in the grounds or turning it on. Then I left the Impress Labs office without my key at lunch to run an errand and came back to a locked office front door. So I tried the main entrance and got as far as the communal restroom (shared with other offices in the building) before meeting the locked back entrance. Luckily there’s a comfy couch in the rest room, so I spent some time surfing on my smartphone until someone returned and let me in.
One of the best features of smart devices such as smartphones and tablets is the freedom to get work done from pretty much anywhere, even the office rest room. In fact, one of the interesting nuggets of information I came across was a USA Today survey shared on GlobalFoundries Facebook Page , that reports the use of tablets on airplanes is almost equal to laptop use.
But I digress (like I said, it’s been one of those Mondays.) I’ve been curating SemiMD’s Experts at the Table Stacked Die Reality Check series (here and here) and Part 3 was posted today. This segment focuses on the temporary bond/debond roadblock, system costs vs. component costs, integrating heterogeneous materials, progress on standards, and when “2.5D and 3D devices will start showing up.”
It’s this last question, and the varying degree of answers, that caught my attention the most. I guess it depends on how you define “showing up.” Ultratech’s Manish Ranjan said for 2.5D “meaningful volume (20 – 50K wafers) is at least 2 years out. TSVs a couple years beyond that.” Scott Smith of Synopsys says the company measures tape-outs, and by those calculations he says “2.5D already is well on the way to becoming useful. For 3D, aside from a couple examples, we won’t see that until 2015.” Smith pointed to Altera and Xilinx as providing “early examples”. (Cue Xilinx promotion of its all programmable heterogeneous and homogeneous 3D ICs now in production and Altera’s heterogeneous 3D IC featuring a high-speed chip-to-chip Interface that the company intends to introduce at 20nm (no idea exactly when), “manufactured using TSMC’s chip-on-wafer-on-substrate process”.)
Mentor Graphic’s Steve Pateras says his company also counts by tape-outs and that this year 2.5D is happening, and next year will be memory on logic. Logic on logic has a ways to go. And Matthias is the most optimistic of all, predicting major players will have production capacity for both 2.5D and 3D by the end of next year (that’s 2013) and Patel concurred, and predicting 2014 to be “a very interesting year.”
On SemiMD’s sister site, System-Level Design, another Experts at the Table discussion takes a closer look at challenges prototyping FPGAs. SLD queried Troy Scott, product marketing manager at Synopsys; Tom Feist, senior director of marketing at Xilinx; Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software; and Ralph Zak, business development director at EVE about FPGA’s being used as a platform for a 3D stack. Feist said that 2.5D has been introduced, and a heterogeneous version with an FPGA and an external SerDes has been released. Where it goes from there will depend on market demand. Scott says it makes sense for hybrid ICs because of the yield benefit. From there, the discussion focuses on software development and the numerous issues there. (But I won’t spoil the ending for you, you’ll have to read it yourself.)
The rest of the week, I’ll be reporting from IMAPS International Symposium in San Diego. Look for me there! ~ F.v.T
