For me, Mondays are about regrouping, getting out of weekend head and into what’s going on in the 3D world. (I confess, I do leave my work at the office!) Mostly I cruise around looking to be inspired. Here’s what was waiting for me today.
Symmetry is an online magazine I’ve never heard of before; probably because it’s about particle physics and how it relates to other aspects of life and science (according to the masthead). I landed there today following a link to an article titled Electronics in an Extra Dimension, which basically is introducing the concept of 3D ICs to its readership, and announce that Fermilab is working with partners (among them Tezzaron Semiconductors) to fabricate prototype 3D chips for applications in high energy physics (HEP). Unlike the 3D ICs we’re familiar with that use TSVs to interconnect one or more die in a stack, what Author Joseph Piergrossi describes sounds more like monolithic 3D ICs, writing that The “3D” term refers to the chip’s layered arrangement of circuitry that allows for shorter connections between the chips elements, as contrasted with a single-plane, side-by-side arrangement. He quotes Fermilab physicist, Ted Liu, who says: “Some people think we just take a chip, cut it in half and stack it, but what we’re doing is architecturally changing things at the design level to take full advantage of the 3DIC technology to dramatically improve the performance.”
Fermilab has been working to implement these 3DICs into “detector components to be used in CMS, ATLAS, the ILC and even in photon science projects.” The findings? 3D is the way to go because it’s a cheaper alternative than traditional 2D design. Now there’s something you don’t hear every day.
Elsewhere in mainstream 3D IC news (did I really just use the word “mainstream” and 3D ICs together?) Cadence has two announcements out today regarding its suite of 3D IC technologies (EDA tools). The first is that “TSMC has validated Cadence® 3D-IC technology for its chip-on-wafer-on-substrate (CoWoS™) reference flow with the development of a CoWoS™ test vehicle that includes an SoC with Cadence Wide I/O memory controller and PHY IP.” Also according to the press release, this is the foundry segment’s first silicon-validated reference flow enabling multiple die integration, and features TSMC CoWoS™ and Cadence 3D-IC technologies to make 3D-IC design a viable option for electronics companies.” (The full press release is here). So by the looks of things, TSMC is working with both Cadence and Synopsys design tools as part of it’s CoWoS reference design flow.
Cadence also reports that its 3D IC end-to-end tool suite was used to implement, analyze, and verify ITRI’s first 3D IC test chip after a year of close collaboration. The test chip is a wide I/O memory stack with TSVs. (full press release).
The Apple/Samsung saga continues with rumors that Apple is winding down its existing contracts with Samsung and will be taking its future A6 business to TSMC. This juicy piece of gossip came from a post on CNET by Brooke Crothers. According to a quote from Gus Richard, an analyst at Piper Jaffray, Apple is working with TSMC at 20nm. All other confirmations come from “unnamed sources.” And neither Apple nor TSMC have commented on the story. If it’s true, it would not only impact TSMC but its other customers, as Apple’s consumes considerably more chips than the foundry’s other customers.
