Because 3D Memory really stands out as an industry apart from 3D ICs, I’ve been collecting some interesting articles over the past few weeks, with the intention of bringing 3D InCites a curated update. Here it is.
In the wake of JEDEC’s announcement that it had released its specification for Synchronous DDR4, the first of its kind to include features supporting 3D stacking, Synopsys’ blogger Navraj Nandra responded to requests for high level information on this interface protocol by posting a Q&A blog and also a video in collaboration with ChipEstimate TV (below)
Unfortunately, according to a post by Chip Design Magazine’s Ed Sperling, Thanks for the Memories, DDR4 may not even be enough to solve the “routing congestion now plaguing complex SoCs” caused by current memory device technologies. Sperling explains that the tremendous performance improvements allowed by DDR2, 3 and even DDR4 are still not enough, and that adding more memory creates its own issues with latency and cache coherency. However, there is hope, and Sperling goes on to provide an update on Micron’s wide I/O DRAM on logic solution, aka the Hybrid Memory Cube (HMC). Luckily, the HMC greatly improves performance, power and real estate issues, has worked out its initial signal integrity issues and has 3 design generations under its belt. HMC currently targets the server market, but hopes are high for the mobile market as well. Get full details here.
But DRAM is not the only 3D memory game in town, as we well know. In Universal Memories Fall Back To Earth (what is it with these word plays?) SemiMD’s Mark LePedus writes about how the quest for a next-generation memory technology that would serve as a “universal memory” — or one that could replace all four conventional memory types: DRAM, NAND, NOR and SRAM — is turning out to be hype. Instead, there are a number of what LePedus calls “universal niches” or a variety of next-gen memory types, among them 3D NAND. He outlines them all here.
In Hynix View on New, Emerging Memories, Christie Marrian, moderator for www.ReRAM-Forum.com, hones in on the company’s various approaches to 3D NAND, as presented by Sung Wook Park of SK Hynix during the Flash Memory Summit held in August. There are 3 approaches in simultaneous development PCRAM (phase change RAM) with IBM, STT-RAM (next gen MRAM with Toshiba and the ReRAM program with HP. Marrian gives a fairly detailed analysis, and then concludes by saying that the most compelling point made by Dr Park is that “any new memory technology will have to either be a drop-in replacement for existing DRAM or NAND products or have such a compelling performance advantage that a ‘system’ will be built around it to take advantage of that capability.”
Toshiba is also moving along in the 3D NAND race with its p-BiCS (pipe-shaped Bit Cost Scalable) technlogy. A recent post by Chris Mellor on the Register, The 3D die stack tack: Toshiba builds towering column of flash, announces that the company will have prototypes available in 2013. and plans to ship in volume by 2015. Mellor explains that unlike 3D DRAM, 3D NAND is not about stacking NAND chips on top of each other and interconnecting them, but rather involves stacking layers of NAND in a single chip. Additionally, in terms of capacity levels, pBiCs is cheaper than traditional NAND when it reaches more than 15 layers. Mellor also talks about Toshiba’s ReRAM technology, which is following a similar roadmap, but will be used in a different memory role than p-BICs. Mellor does a great job explaining this technology in layman’s terms. It’s a recommended read.
Interested in learning about the first working 3D NAND flash memory? Then be sure to attend this year’s International Electronic Devices Meeting (IEDM), where Macronix researchers will be describing 3D NAND flash memory at sub-40nm feature sizes.You can read more about it here on Solid State Technology.
