But first, a 3D history lesson thanks to a recent SemiWiki blog post, Hybrids on BeO then, 3D-IC in silicon now, in which blogger Don Dingee recalls lessons learned from working with hybrid microelectronics assemblies, and how they apply in the world of 3D. Calling 3D ICs “the modern version of hybrids” he notes that “This isn’t just to get more stuff in less space by better utilizing the Z axis, as the 3D name would imply. It’s about using the right process for the right function.” He also reminds us that 3D isn’t just solution for scaling to future nodes – but also provides options for analog devices built on “mature, low risk, low noise process nodes.” It’s food for thought and worth a read.
We hear a lot about power and reliability being issues that can be solved by 2.5D and 3D architectures, but we don’t hear a lot about why. I always assumed it had to do with cramming more technology into the system (smartphone) itself, but it turns out it has more to do with the issues for SoCs themselves as they are scaled to 28nm and beyond. SemiWiki’s Paul McLellen explains it pretty well in his post, Power and Reliability Challenges, which he wrote after attending Ansys/Apache Seminars on Dimensions of Electronic Design. What’s most vital, he says, is that the chip, package and system are all designed together, to determine whether or not design in 3D TSV chips or 2.5D interposers.
Thermal issues are also still being hammered out, and in his blog post, ICECool puts 3D thermal issues back in focus, SST’s Dr. Phil Garrou reviews current efforts at managing thermal issues in 3D stacks. While reiterating his position that “thermal will not be a roadblock for 3D ICs” he references an article by Herman Oprin that suggests hot spots, due to reduced thermal spreading as a result of die thinning combined with using adhesives that have low thermal conductivity, need to be reckoned with. Luckily, DARPA’s BAA 12-50 ICECool effort is working to solve this issue. Garrou explains DARPA’s work in chip-level heat removal that combines interchip microfluidic cooling with on-chip thermal interconnects. ~ F.v.T.
