Unfortunately, it’s not enough to have customers clamoring for them (3D devices), or that processes, materials and equipment are ready (or almost) and waiting for implementation to fine-tune them; and that EDA and test vendors working feverishly to fill in the design and test gaps; nothing will roll until the supply chain says it rolls. And according to Karen Savala’s (SEMI) recent article posted on the SEMI Website titled Supply Chain Readiness in an Era of Accelerated Change “there are no collaboration models to solve this foundry-OSAT-IDM and fabless chip matrix for complex, multi-chip packages” and while “SEMI standards are addressing many supply chain, equipment and materials issues, market demand and business models must continue to sort themselves out before 3D chip stacking can widely penetrate the industry.”
****We interrupt this post to bring you the latest update on 3DIC Standards from SEMI. The first 3D IC Standard has been approved and will be published as SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. You can read all about it, and related progress here. Now on with the rest of my thoughts.***
Personally, I was surprised to hear some of this. The part about business models sorting themselves out I get, but it sure seems that market demand is there. (If you don’t believe me, just ask Xilinx, Qualcomm, Hynix, nVidia, GlobalFoundries and TSMC). And wasn’t it customer demand that inspired GlobalFoundries to add capacity for 3DICs in Fab 8 back in April, and why TSMC is hell-bent on doing it all, end-to-end?
It seems various supply chain collaboration models are being discussed and shared ad nauseum by foundries and packaging houses alike (most notably, GlobalFoundries, UMC, ASE, Amkor and Powertech) with a general consensus being that all emerging models will co-exist, and will be based on the needs of the customer. As Ann Steffora Mutschler writes in a post titled “The Changing Role of the OSAT,” on SemiMD, “OEMS are gaining dominance in the ecosystem.” She interviewed Raj Pendse, of STATS ChipPAC, Ron Huemoeller, of Amkor, for the OSAT perspective and Bob Patti, of Tezzaron, from the user perspective. All agreed that the customer will likely dictate who does what, and there will be different scenarios emerging. Mutschler quotes Amkor’s Ron Huemoeller, who explained a paradigm shift in customer collaboration, where customers are involved from the design stages to taking products to market.
Perhaps there are still expectations that there will be one standard order of procedure that shakes out? It’s good that progress is being made by SEMI and SEMATECH with regard to standards for equipment, and materials, but I’m not convinced the supply chain itself can expect to adhere to one standard model, particularly if its the one TSMC is suggesting.
ITRS Roadmaps
Talk of Standards leads me to think about the much-discussed, biannually updated document that dictates the course of semiconductor manufacturing. I’m talking about the ITRS Roadmap. As is the case with SEMI Standards, the ITRS Roadmap was primarily established for chip manufacturing (aka front-end manufacturing). Its only in recent years that attention has been paid to the back-end, because lets face it, front-end processes lend themselves to standards and roadmaps much more than back-end processes, because there’s not all that much variety involved. On the other hand, the back-end is all over the place, and much more difficult to nail down to standards and roadmaps. Therefore, it’s interesting to theorize how Standards and the ITRS roadmap affect the course of 3D IC commercialization.
Unfortunately, I did not attend the ITRS Roadmap workshops during SEMICON West, but luckily SST’s Meredith Courtemanche did and generated enough back-end material to populate two posts. Her general observations on back-end packaging and MEMS can be found here. with more in-depth coverage on roadmapping “more than Moore” here. Some key takeaways from both posts:
- With regards to ramping to TSV, Bill Bottoms, ITRS spokesperson for back-end technologies, noted that in comparison to the ramp for flip chip and Cu wire bond, which took 20 years, TSVs are moving fast with only 6 years logged in. He also corrected a common misconception that the thinning process itself is not the concern of the roadmap, but how to handle thin wafers/die is.
- 3D test is getting lots of attention in the ITRS roadmap updates, with a whole chapter added on 3D device test added last year (2011) and a 3D test table illustrating work left to be done on the drawing board for 2013. Included on that that list are test handling changes and wafer probe frequencies due to the known good die (KGD) issue.
- Advanced wafer-level and 3D packaging, MEMS and related microelectronic technologies comprise what is called “more than Moore” and are more difficult to roadmap than standard CMOS processes. It’s not just about scaling anymore, reports Courtemanche. It’s about both scaling and diversification, and is application specific. So ITRS has had to adapt its roadmapping methodology for “more than Moore”, adding in an application consideration to the process.
Here’s what I wonder most about the ITRS Roadmapping process. Do we have a chicken and egg situation here? Roadmapping is supposed to layout a path of progress, right? What if 3D ICs come online ahead of schedule, before the roadmap has ironed out all the issues? Can the roadmapping process actually delay the commercialization of 3DICs? Post your comments here! ~F.v.T.
