I was on the phone with Herb Reiter yesterday, who told me he’d been busy this week thanks to the Hot Chips Conference (Aug 27-28, Cupertino CA). I’d been reading about it here and there, but hadn’t made the trip from Phoenix myself. “Should I have been there?” I asked. “You should have been there Monday for the Xilinx tutorial on Die Stacking.” Apparently I missed a very comprehensive tutorial session featuring presentations from AMD, Amkor, Qualcomm, UMC, and Xilinx explaining how 3D-ICs built. Unfortunately, I can’t seem to find anything that’s been written about the tutorial, (Please send it my way if you have!) but there are a couple reports worth mentioning from other bloggers that is of interest to 3D enthusiasts.
Steve Leibson (EDA Insider) was there, and reported that the Penwell SOC contains a 3D package-on-package (3D PoP) that stacks LPDDR2 SDRAM on the SOC to reduce both the processor/memory footprint, but the power requirement as well. You can read about it and see some cool images here.
And here on Rage3D, blogger James Prior reports on AMD CEO Mark Papermaster’s Hot Chips keynote about what the AMD refers to as the “Surround Computing Era.” We’ve been hearing various versions of this concept over the past few years. Some call it ubiquitous computing, and others call it “The Internet of Things” (my personal favorite). it seems once again the current drivers for increased computing power are being identified as the client and the cloud (otherwise known as smartphones, tablets and high-end servers). According to Prior, one of the ways AMD intends to address this is through die stacking – both 2.5D and 3D – depending on the application.
John Blyler, blogger for ChipEstimate, posted his tweets for the week from Hot Chips,with a promise for more editorial next week. So I’m waiting to see what he comes up with.
More on Stacked Die Reality Check
Last week, I summarized SemiMD’s “Experts at the Table” discussion featuring Manish Ranjan (Ultratech), Thorsten Matthias (EV Group), Steve Pateras (Mentor Graphics), Steve Smith (Synopsys) and Sunil Patel (Global Foundries). This week, SemiMD posted part two of this discussion (it’s not titled “part two” in the title, so unless you start reading it, you might think it’s the same post, based on the title. But it’s not.)
This segment of the discussion addresses the panelists differing viewpoints on how quickly stacking will happen: Ranjan says below 14nm for TSVs is most likely; Matthias says at 22nm, the modularity advantages of 3D stacks offers system level cost savings; Patel agrees, adding that if you focus on individual layers it may seem cost prohibitive, but in reality there’s system level cost savngs (Sunil and Thorsten, you’re singing our song!). Pateras sees it first for heterogeneous stacking and later, perhaps, for logic. Other topics of discussion were liability issues and when EDA comes in. Click here for the full article. ~ F.v.T
