Tish LeBlanc, from TI: “How’s your SEMICON West going?
Me: “I was just trying to put it into words.”
It’s Thursday, and another SEMICON West (my seventh) is winding down, and its the first time I’ve found time to write since Monday evening. As always, it’s been a whirlwind of sessions, editorial appointments, networking events, and for the first time for me, video interviews. When presented with the dilemma of where to fit in writing time, I decided the opportunity to interface with industry peers takes precedent – the writing (me) and reading (you) can happen later (as in over the next week or two).
Two of the best additions to this year’s event? First, free wireless in the Moscone Center, which made live tweeting a possibility, which you may have noticed if you follow my twitter feed, (@francoisein3D) and I took full advantage of it during most of the sessions.
And second, EV Group’s Industry Recovery Brunch this morning, complete with Mimosas and Bloody Mary’s. It really was a lovely way to start the wind-down day. It also brought more people onto the floor at opening time. Next year, I’m going to try and institute “Casual Thursday” where we can all lose the suits and ties, and wear jeans and comfortable footwear.
For me, Wednesday’s greatest challenge was how to fit four receptions in a two-hour window. I managed 3 out of four, and have the photos to prove it. Of the three I attended, I have to give kudos to SPTS, who’s Olympic themed event added some playful diversion with virtual sporting events and friendly competition.
In any case, here’s what I’ve been hearing over the last three days with regard to 3D integration technologies. There is no disagreement that 3D is needed, that it is one of the key enablers for system scaling, and that it is coming (many seem to even say it’s already here.) Three remaining challenges, according to Ultratech’s Manish Ranjan, are thermal, cost and supply chain issues. With regard to cost, Manish said it’s really a function of demand, and that as the demand goes up, the cost will come down. What we really need to pay attention to, he says, is the cost/performance ratio. Is the improved performance worth the cost? What other choices do we have?
3D and Ubiquitous Computing
In his Keynote address on ubiquitous computing (another term for the “internet of things.”) Intel Fellow, Shekar Borkar noted that as system performance and parallelism continues to increase, power and energy will continue to be a challenge. He said reducing energy requirements is the challenge of the decade, and that energy scaling will make integration affordable. Technology can help. The 22nm 3D TriGate transistor provides one solution for energy reduction. In the Memory area, Borkar says a new DRAM architecture requiring a large number of I/Os. Here, “the 3D guys came to the rescue, you gave me 3D technology and that’s how I’m going to do it.”
3D Ready for Take-off?
At Suss MicroTec’s 3D workshop, Jean-Marc Yannou, of Yole Développment, delivered the market research firm’s “summer status” report for 2.5D and 3DICs in which he identified technology segments for 3D interposers. Fine-pitch interposers will be used for high-end, and high power logic applications, requiring the finest design rules. Coarser interposers (larger TSVs) are suited to analog applications and low power applications.
Eric Beyne, of imec, provided a technology update, reporting that there is clear industry convergence on Cu TSV processing route, via middle, 5x50um vias. He indicated a key challenge for 3D integration is lack of a suitable wafer carrier system for wafer thinning with high precision and compatible with further backside processing. Additionally, as the technology matures, there will be a stronger emphasis in die-to-die stacking at progressively smaller technology nodes (40um, 20um, 10um, etc.)
More on Glass Interposers
I saw two presentations on Georgia Tech’s 3D Packaging Center’s efforts to reduce the cost in 2.5D and 3D IC packaging by developing alternative processes, materials and tools for manufacturing. One was presented by Venky Sundaram at Suss’s workshop, the other by Rao Tummala, at SEMI’s 2.5D and 3D Packaging Techxpot. Georgia Tech is developing panel-based processes using lasers to form “holes” through PolySi and/or glass wafers and panels. Tummala says in wafer form, there’s a 2x cost reduction over Si, whereas in panel form, there’s a 10x cost reduction.
Why glass? Sundaram claims glass has ideal properties such as ultra-high resistivity, ultra-low electrical loss, low dielectric constant, and a tailorable coefficient of thermal expansion (CTE) for surface mount to board interconnect. “It’s the best of all worlds in one material,” said Sundaram. “It has the lithographic precision of Si, lowest loss of ceramic, and large panel/low cost advantages of organic substrates.” However, it is not without challenges, namely the brittleness of glass and low thermal conductivity, as well as engineering barriers such as a lack of high throughput tools and processes for through glass vias (TGV) holes, and TGV reliability.
2.5D a 3D Packaging Landscape
Also at the SEMI 2.5D and 3D Packaging TechXpot, John Xie of Altera talked about the company’s work with TSMC on chip-on-wafer-on-substrate (CoWoS). He said that a CoW 1st approach holds the best process yield potential because it exhibits favorable ubump joining, is large-die compatible, avoids thin wafer handling, and can leverage know-how from wafer level processes, but requires considerable investment in developing wafer-level tools.
Ryusuke Ohta, of Fujitsu Semiconductor, said when choosing between 2.5D or 3D, you have to look at the trade-off of bandwidth advantages vs. thermal management. He said 2.5D offers limited bandwidth, but has flexible thermal management. On the other hand, 3D has higher bandwidth but thermal bandwidth issues. Fujitsu is investing in system-in-package (SiP) using Si interposer technology.
The session concluded with a panel discussion, during which attendee Keith Newman, of Hewlett Packard, declared that he was “super excited about 2.5D and 3D products.” But asked “will they survive once they come off the manufacturing floor?” One of the panelists, Dave Stepniak, of TI, responded that indeed, the end devices will need to match what’s out there in terms of reliability, and the challenge will be with temperature cycling. He said greater collaboration within the industry is needed for new materials. While on the other hand, Rich Rice of ASE, also a panelist, said that although it requires putting another layer of interconnect, copper pillar interconnect is very reliable, and putting advanced die on a silicon interposer rather than a substrate means the thermal expansion is different, and could ultimately perform better than what’s out there.
This is the tip of the proverbial iceberg. One thing about SEMICON West, it always provides me with an abundance of content opportunities. So there’s much more to come. ~ F.v.T.
