Note to self: no more graduations/college orientations/vacations in the month of June. There are way too many events in 3D and I missed so much while I was off focusing on other things! Lucky for me, people writing and blogging about 3D technologies are coming out of the woodwork, and so as I catch up on my reading, I’ll point you to some of the key points made by my capable colleagues in the 3D blogosphere.
Working in date order, the first event of note was the IITC 2012, which took place June 4-6 at the Double Tree Hotel in San Jose, CA.
Michael Fury posted a 3-part conference report in Solid State Technology, providing highlights of selected technical presentations.
Mike Mayberry, VP Components Research of Intel delivered the opening keynote, and according to Fury talked about the continuing quest for “smaller, faster, cheaper joined by longer battery life” through CMOS efforts, which will only end when “we run out of ideas.” Mayberry reportedly said that “one new idea is the notion of stacking devices themselves, rather than remaining constrained to a single layer of silicon.” New idea? Really? Sounds just like 3D ICs that the rest of us have been talking about for years.
Other 3D mentions are scattered throughout the report, with most of the attention on Day 3’s post. From Fury’s lead and initial commentary – “Subramanian Iyer of IBM started the day with an invited talk on scaling in the 3rd dimension (not to be confused with The Adventures of Buckaroo Banzai Across the 8th Dimension) and prospects for silicon interposers and 3D integration. His retrospective introduction harkened back to IBM’s multi-layer ceramic thermal conduction module (TCM), which he re-characterized as an early model for today’s silicon interposers.” – it seems like he’s not a big believer in 3D himself, but I could be wrong.
Here’s what I got mostly from this coverage. This was one content-rich event, and it’s nearly impossible to get to the meat of any of these presentations by reading a conference report. If you really want to get the most out of IITC 2013, I suggest you put it on your calendar for next year. It’s taking place in Dresden. Dates and Call for Papers will be posted on 3D InCites when they are available.
SemiMD’s Mark LePedus also referenced Mayberry’s keynote at IITC 2012 in his recent post, Challenges Mount For Interconnect in which he talks about Mayberry’s concerns with scaling below 30nm as being a challenge for PVD, with the solution being “ALD or other solutions that or other methods which allow high surface migration to deliver conformal films.” While LePedus cites 3D TSVs as one solution to the problem, he says “advanced chip-stacking has a multitude of challenges and is still a few years away from mass production.” Instead, he says “the industry is stuck with planar and must make advances on two interconnect fronts: metallization and low-k dielectrics.” He then goes on to detail the different approaches being developed and their respective challenges. This begs the question, are these challenges just as daunting as what 3D IC is facing? Might they take long to develop as just pushing forward with 3D ICs?
Overlapping and on the heels of IITC 2012, was DAC 2012, which took place at the Moscone Center in San Francisco. Cadence blogger Richard Goering did a stellar job of covering the 3D Panel, Is 3D Ready for The Next Level. Rather than a technical focus, this panel focused more on the business advantages of 2.5D and 3D ICs.
Apparently I missed a relatively heated debate by some of the industry’s reigning authorities on 3D. But not to worry – I feel like I was there after reading Goering’s observations. Some of the more interesting nuggets:
In response to a question, “what is 3D technology good for?” Intel’s Shekhar Borkar, responded that it is “not good for the integration of logic to reduce interconnect delay, but it is good for heterogeneous integration, and for reducing system-level interconnect energy.”
In response to the age-old question, “when will volume production start,” the responses were as varied as the companies represented by the panelists (TSMC, Cadence, Xilinx, Intel, and IBM). The biggest standoff was between Borkar and Subu Iyer, of IBM (man, that guy gets around on the conference circuit these days!). Borkar apparently stated that 3D ICs will start in the commodity market, while Iyer believes it will start in the high-end and trickle down. (I guess it all depends on whom you work for). I don’t want to ruin the ending for you, so be sure to check it out. Trust me, it’s well worth the read.
Incidentally, Daniel Payne, of SEMI Wiki, visited the exhibitor floor at DAC and offered a couple product overviews, of particular interest to 3D followers is 3D Thermal and Mechanical Stress for IC Packaging.
There are a few more events that I need to catch up on, and this post is getting rather long, so I’ll stop here and pick it up next time. ~ F.v.T
