Really, it all boils down to simple economics. I’m referring to WHY the road to 3D is taking as long as it is to reach commercialization. We’ve convinced the engineers of the technology benefits. Now it’s time to convince those who hold the purse strings: the management.
I had an interesting discussion about this with Herb Reiter upon his return from Tokyo where he moderated a 3D panel at the GSA/SEMATECH Memory+ Conference there. He said while there were no “Aha!” moments to report, the message clearly conveyed by the panelists was that the design and manufacturing companies are committed to playing their position in the 3D ecosystem.
“The whole food chain is clearly ready to work with the customer in whatever is required, and they realize that 3D is a must have,” noted Reiter. This particular ‘food chain’ comprised panelists from Amkor (Ron Huemoeller), Cadence Design Systems (Fumiyasu Hirose), TSMC (Dr. Toru Ogawa), IBM Microelectronics (Dr. Subramanian (Subu) Iyer), Tokyo Electron (Dr. Gishi Chung) and ARM’s Hsinchu Design Centre (Tim Whitfield).
It’s pretty clear to everyone that although 3D technology has its challenges, there’s nothing that can’t be solved at this point by good engineering. As Reiter sees it, the problem 3D is running into has more to do with the current state of the global economy. “We’ve been in a recession for four years and companies are squeezed for profit.” He noted. “As an industry, we have enormous challenges to address and limited funds. Our capitalistic business models require us to show profits, and CEO’s aren’t able to fund developing 3D technology as quickly as they would like and have to slow down engineers in their zeal to ramp 2.5D and 3D production.”
Reiter explained that our semiconductor industry as a whole always had too many challenges and opportunities on the table and too few liquid assets. The recent recession and the slow demand recovery make this situation even more difficult for management. Among the simultaneously occurring challenges for our industry are 2.5D and 3D-ICs, EUV technologies, the transition to 450mm wafer sizes, and the need to rebuild domestic manufacturing rather than expanding offshoring. While all of these are pulling at the same pot of funds, Reiter cautioned me against presenting them as an either/or dilemma for our industry. None of them should be sacrificed for the benefit of the other. All are important to industry growth in their own way. Setting priorities for allocating funds and engineering resources is basically an application-specific dilemma, with different players making decisions to strategically invest in what will benefit their companies, share-holders, employees and, of course customers, the most. So how do you establish priority of addressing these economic pulls? Depending on a company’s customer requirements and strategic business plans, some management will invest more in 3D than in another space.
Let’s briefly analyze key benefits and challenges of the technologies mentioned above:
Transitioning from 300mm to 450mm wafer sizes will offer significant unit cost benefits to better compete in the cost-sensitive consumer market and other high volume applications, but significant capital will be needed to retool factories. 450 mm is a priority of the top tier companies. That’s why Intel is motivated to invest in 450. In fact, IBM and Intel are building a factory in upstate NY to develop 450 wafers, tooling and a 450mm manufacturing flow.
The deal with EUV lithography is that without it, we won’t be able to write small enough feature sizes on the critical layers that are expected to be designed in the future. But, again, development costs of EUV are proving to be prohibitive for all but the largest manufacturers. So as it stands, EUV will be ready for deployment at the 10nm node, and not sooner. Lack of EUV lithography will impose yield- and cost constraints. Additionally, 2D systems-on-chip (SOCs) are a steeper challenge due to their die sizes and the fact that we’re most likely not improving performance or lowering cost per transistor, but are in fact dealing with larger interconnect delays.
And then there’s 3D, which requires more precision not only from the fab side but the assembly side as well, which means an increase in assembly equipment costs. Historically, the steps that took place at the OSAT seemed to be low-cost manufacturing steps. Therefore, OSATS have always had to live with small profit margins while foundries had larger profit margins and could afford more expensive equipment. “Assembly and test of 2.5D and 3D-ICs are an opportunity for OSATS to get creative and find ways to get larger margins required for capital expenditure,” noted Reiter.
As it turns out, OSATs have already plenty of experience with die thinning, stacking die vertically and testing partial- and completed stacks. Wire-bonded SiP (System-in-Package) configurations have been in volume production for some time and require these skills. The new generation of 3D-ICs with through silicon vias (TSVs) seems to be solving yield- and reliability problems that existed in SiPs. Some experts even say that TSVs are making OSATs’ lives easier, because wire bond requires full size I/O to charge and discharge the bonding wires. TSV interconnects allow reducing the I/O buffer drive and saving power dissipation, silicon area and possibly package cost.
And the real beauty of 3D is that you’re combining proven building blocks in die form— power management chips, microprocessors, memories, FPGA and analog component — that already exist in volume as stand-alone ICs. Combining separate analog and logic die into one package is more cost-effective than designing and manufacturing a super chip, using many more masking layers. That’s the real vision of 3D technology and message to the CEOs. “3D is becoming a system design technology; it’s not just another IC design technology because you can put so much functionality into a package, combining what was once a bunch of chips mounted side-by-side on a circuit board,” explained Reiter.
While all new technologies tend to be more costly at introduction, compared to the component cost of the proven solutions they are destined to replace, technology advancements and cost reduction efforts can and will narrow this gap quickly.
When comparing 3D-IC solutions on the system level – accounting for board-space savings, reduced cooling cost, smaller and lower cost power supplies or batteries as well as the value of added convenience and user friendliness – 2.5D and 3D-ICs are justifying the investments needed to adopt these system-level solutions.
2.5D and 3D-ICs will allow today’s semiconductor vendors to provide system-level solutions in an IC package and grow their revenues and profits by adding to the current $300B semiconductor TAM part of the $2,000B system TAM. ~ F.v.T.
