So there I was, listening to Eric Beyne talk about the importance of co-developing advanced CMOS and 3D ICs because one directly affects the other, when my thoughts turned to once again to FinFets (is this what he means by advanced CMOS?) I wondered whether these so-called 3D transistor structures would affect the planarity of the wafer, thereby making stacking difficult. In my naiveté, I did what I always do. I asked. Eric explained that FinFets aren’t really 3D, that Intel just adopted the 3D lingo with its TriGate announcement (or maybe it was the journalist who wrote the first story and called it 3D technology to grab interested readers). In any case, he explained that FinFets go through a CMP step to make them planar, and can be stacked using whatever interconnect technology is called for the specific application. Good to know. (Seriously Intel, get your own buzzword.)
This exchange of information took place in the second panel session of 3D in the Submicron Era during last week’s SEMICON West 2011 in San Francisco. It got me to thinking how messages can be misinterpreted when you don’t have the right information or the whole picture. I attended all three packaging focused sessions at SEMICON West — Heterogeneous Integration with MEMS and Sensors, Contemporary Packaging, and 3D in the Submicron Era—hoping to get a holistic perspective on TSV adoption. Instead, I found that different stories are being spun about TSVs, based on the ultimate motivations of speakers and companies represented. (More often than not, the real story of the day is not the material being presented, but the discussions they spark during the panel sessions and among the attendees after the event takes place.)
Heterogeneous Integration
In the Heterogeneous Integration with MEMS and Sensors session, Keynote Speaker Rob O’Reilly, Analog Devices, said that the beauty of TSVs is that there can be a combination of solutions for heterogeneous integration with ICs and MEMS devices; however he’s not convinced that anyone can sell this because of cost. According to Jan Vardaman, it’s the cost/performance tradeoff that determines the adoption of each application. So at what point does fulfilling performance needs outweigh the cost of TSV? It’s all about value proposition and will happen in MEMS on a market by market basis. Reilly said that heterogeneous solutions will help reduce size and cost of sensor fusion applications and will eventually require TSVs and micro-bumping. “High performance sensors are set to transform an incredibly diverse scope of new applications including medical, industrial, automotive, and military.” said Reilly. The first mass adoption of the TSV market will be high performance devices involving MEMS and image sensors, integrated in the back end using silicon interposers. Automotive is one of those markets that will take its time, because it’s not driven by miniaturization, noted Horst Theuss of Infineon. “Reliability comes first. It’s not negotiable.” he noted, adding that we’re at least 5 years away from TSV for automotive sensor packaging.
Contemporary Packaging
I sat down in the Contemporary Packaging session with some mild trepidation. What was this new term coined especially for this event? What exactly are contemporary packages? Are they beyond Advanced Packaging? Turns out, contemporary packaging refers to what’s in production now. It occurs to me that the term could be interchangeable with legacy packaging or conventional packaging, but they lack a certain joie de vivre. They don’t draw attendees to the presentations. Calling something contemporary gives it relevance in the current markets. Contemporary packaging, I learned, refers to innovations in what makes up 70% of the market today, including copper wire bonding, copper pillar bumping, and package types using updated processes in the existing infrastructure for low-cost and faster time-to-market alternatives.
The speakers during this session noted that while 3D technologies existed mostly in conference papers alone, contemporary packaging is providing innovative, low cost solutions right now. It seems to be the belief among the OSATS providers represented on the panel (Mike Ma from SPIL and Fernando Chen from STATS Chip PAC) that this is what will carry the industry forward for quite a few years. Ma predicts that by 2014, wire bond will still dominate the overall IC market with 84% and that by 2012, wireless-related IC packages will be dominated by wafer level package and flip chip. Chen says the benefits of wire bond (mature technology, high yield, reliability cost effective, well established infrastructure) make it worthwhile to still innovate. He sees challenges for wire bond beyond 40nm that will require addressing design and pad geometries, equipment and materials. However Doug Yu of TSMC says that although advanced packaging technologies are initially higher cost, that risk is often reduced with the product ramping. Contemporary packages are good for most cost sensitive products and continue to drive costs lower, but the risk of being replaced remains. TSMC’s strategy is to innovate for advanced packaging with disruptive solutions such as fan-in WLP, fan-out WLP, and TSVS. “What are today’s advanced packages are tomorrow’s contemporary packages,” he says. “In the long run, people may regret not working on advanced packaging solutions sooner.”
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2.5 and 3D Integration
The first panel of the 3D in the Submicron Era seemed to be intent on delivering the message that 2.5 silicon interposer technology is currently a viable alternative to 3D IC. Part two of the message was that although ultimately 2.5D and 3D will coexisit, using passive silicon TSV interposers will delay the need for true 3D IC. Something in this message seemed lacking to me, so I bounced my idea around the receptions. I got lots of affirmation for this, so feel confident in sharing this with my readers. Consider that applications for this product use large die FPGAs targeting the telecommunications and networking industries, can it find its place in the mobile market? If not, then it’s not a viable alternative to wide I/O DRAM on logic for handheld mobile devices and media tablets; the killer app for 3D TSVs. Along the same lines, copper pillar bumps may solve certain functionality issues, the technology is limited to stacking two die. The only way to get the level of performance at lower power for high-end smartphones and tablets while solving the memory wall issue is to use 3D TSVs. Therefore while 3D TSV alternatives currently meet the needs for certain applications, they will undoubtedly meet their limitation. Once 3D TSVs arrive on the scene, they’ll be limitless in their applications.
So in reality, when it comes to advanced packaging, 2.5D, 3D integration, and TSVs in passive interposers or active CMOS, definitive answers are hard to come by. It’s important to consider the source. Companies tend to have their own agendas; it’s next to impossible for them to remain objective. They have to spin their data and roadmaps to appeal to the markets they serve. The packaging market is much more diverse than the CMOS market. To assume that any one perspective is the right one is to mistake partial information as fact. There’s 2200 different types of advanced packages currently available on the market. While consolidation is inevitable, it’s likely that there will be lots of peaceful coexistence among contemporary, advanced, heterogeneous and 3D IC technologies for years to come.– F.v.T
PS: Thanks to Roger Quon of SEMATECH for the snappy title. I told you I’d use it and give you credit!
