Will the path to 3D integration be evolutionary or revolutionary? Will 2.D interposer technology be the only route or is “true” 3D integration inevitable? These discussions and debates have taken center stage at most 3D events over the past few years. At this year’s GSA’s Memory Conference on March 31, which focused on 3D architectures, the debate continued, but it seemed that the two camps were actually listening to each other. More than ever, there seems to be consensus about a few things: Ultimately 3D integration with through silicon vias (TSV will be the ONLY cost-effective way to achieve high I/O DRAM + Logic stacks; however, 2.5D integration with silicon interposers is the most viable step to take next, while standards and processes are being hammered out for full 3D. Moreover, it looks like silicon interposer technology will be more than a bridge technology as it becomes a vital component to 3D heterogeneous system integration.
This was the first time I’d attended the GSA’s Memory Conference, and it was interesting to get some perspectives on industrialization of 3D from the manufacturers. Because when all is said and done, the buck stops there. They are the ones who have to make that decision to adopt, and it doesn’t so much matter that a technology is conceptually possible, reliable, and meets all the requirements. What matters most is that there’s a compelling technology application that outranks the issue of cost. Consider this: Samsung demonstrated DRAM stacks using TSVs in 2009, and in March of 2010, Elpida announced they would begin production of 3D stacked DRAM and yet here it is April 2011 and…..nothing.
Kyowin Jin VP, Product Planning, Worldwide Marketing & Sales, Hynix Semiconductor, Inc, explained that using TSVs in DRAM memory is motivated by the technology benefits rather than cost. However, benefits to DRAM stacks alone are not compelling enough; but when you add in the benefits of stacking that DRAM cube on a logic stack, the technology benefits make it worthwhile. According to Dr. John Lau, Fellow of Industrial Technology Research Institute (ITRI) cost is always most important. The prediction was that DRAM TSV stacks would happen before passive silicon interposers. “Everyone was WRONG! Passive interposers will be in production before the memory chip,” He noted. “Whoever published that roadmap was 99% wrong.” Since Samsung and Elpida made their announcements, nothing has shipped. Moreover, Elpida didn’t have a pilot for staking memory chips.
So where DRAM was all the buzz last year, now it’s wide I/O DRAM on logic stacks that offer the compelling benefits to go with 3D TSVs. According to Yuan Xie, Pennsylvania State University, wide I/O DRAM demonstrates the bandwidth benefits of 3D for future Quad High-Definition TV (HDTV) applications.
In the meantime, 2.5 silicon interposer technology has received a hero’s welcome and all believe at the least, it is the next logical step towards 3D IC. Lau differentiates between 3D silicon integration and 3D IC Integrations. He predicts passive interposer technology will be used the most in the next ten years while the kinks are worked out of “true” 3D. Active interposers with TSVs need an ecosystem, EDA tools and business models. However, he also says that 3D silicon is the way to go to compete with Moore’s law, and he industry should strike to make this happen, but realistically, were looking at 10 years before it’s in production.
Here’s what I keep wondering though; while there are clearly technical benefits to migrating to 3D ICs, ultimately does it matter to the materials and equipment manufacturer whether TSVs are used in passive interposers or active 3D IC stacks? Either way, their tools, processes and materials for fabricating TSVs are still needed. So why all the debate? Seems like either way, it’s a win-win. ~ F.v.T
