Things have been pretty crazy lately, what with wearing several hats and all. I spent two days in Silicon Valley last week visiting some companies on behalf of Chip Scale Review, and also at SEMI for an Advanced Packaging Committee meeting for SEMICON West to hammer out the 3D program. When I wasn’t in meetings, I was working on a project in my latest role as principal analyst, Advanced Packaging Technologies, for MEMS Investor Journal. What’s interesting about all this variety, is the multitude of venues it opens up for sharing all this information, as well as providing me with more ideas to write about here.
For example, I met with Scott Jewler, president of the US division for Taiwanese OSAT, Powertech Technologies Inc (PTI). I was excited to learn about PTI’s strategy to invest in 3D TSVs for DRAM applications, as Elpida and Toshiba are big customers. PTI also handles ATE for memory module maker, Kingston. Jeweler says that in the last 5 years, PTI’s memory business has exploded, with 35% CAGR, putting them at number #1 for OSATS in the Memory sector, and #5 overall.
You might remember a recent announcement of collaboration between UMC, Elpida, and PTI to develop die stacking technologies. Die stacking technology. “We believe it’s a highly innovative model,” said Jewler. “DRAM is homogeneous and an early adopter of TSVs. Partnering will enable PTI to be in volume production early while other OSATS are waiting for logic to be involved.” Jeweler explained that by bringing UMC into it, they’ll have a structure that also supports logic + memory applications. This way, the company is well positioned to scale for pure DRAM stacks, and will be able to deploy technology for logic plus memory. This was all very interesting, as Elpida’s been talking about its plans for 3D TSV DRAM for well over a year now. Maybe we’ll actually see forward movement.
PTI’s a fairly young company, (est. 1997) that’s been fairly quiet in the media up until now. But its ready to make a splash in the US, so expect to start reading and hearing a lot more about them. In fact, I’m working on a more in-depth interview article that will be published in the March/April issue of Chip Scale Review.
Speaking of progress in 3D TSVs in DRAM, Micron’s also making noise now as well, and is reportedly close to revealing it’s “hybrid memory cube”, having already built working prototypes stacking memory on logic using TSVs. The company claims this technology will solve the “memory wall” problem that’s plagued the industry. The logic portion is a memory controller that Micron execs say will deliver 20X the DRAM bandwidth directly to the processor. Plans are to go to volume production by 2013. You can read more about it here.
Another thing I noticed from various meetings, this 2.5D silicon interposer thing has really taken hold. In fact, you can expect it to be one of the hot topics covered in the 3D program at SEMICON West. The 3D and Advanced Packaging program is starting to take shape as well. I don’t want to reveal too much until we’ve firmed up the content, but over the next few weeks we’ll be making some announcements.
No doubt we’re heading towards exciting times. It’s a lot to keep up with, but we’re on it! And in my spare time, I think I’ll take up juggling. – F.v.T.
