This column by Francoise von Trapp appeared in the Jan/Feb 2011 issue of Chip Scale Review It sums up a lot of what was said at various 3D IC events over the past few months.
A year ago, there were still skeptics in the room at the annual 3D Architectures for Semiconductor Integration and Packaging conference, sponsored by RTI’s Tech Venture Forum. This year, not a single hand went up when Phil Garrou asked if anyone doubted that through silicon vias (TSVs) would be industrialized. It seemed everyone has reached a consensus: 3D ICs with TSVs are the way to go to achieve the performance, power, form factor and cost requirements of next generation semiconductor devices. But this consensus wasn’t unique to this event, and it isn’t just the R&D institutes that are banging the 3D drum. Major fabless, foundries, IDMs and packaging houses have all taken up the call to arms. (Full Story)
