I just read Mark LePedus’ (EE Times) coverage of the 3-D Architectures for Semiconductor Integration and Packaging last week in Burlingame, and I was wondering if we’d both been at the same event, or was he just not paying attention? TSV not ready to for prime time? I beg to differ.
While I concur that Synopsys’ Antun Domic did a good job painting this particular picture for 3D TSVs; I would hedge a bet that it’s more due to their cautious approach to tool development, rather than an accurate snapshot of what’s really happening. At the same time, Domic’s comment that 2.5D IC implementation flow (package, silicon interposer, and die co-design) could be accomplished in a relatively small time frame makes sense, and a phased approach is definitely something worth considering. Regardless, it doesn’t reflect actual state of TSV progress.
In fact, the other keynote presenters (Subramanian Iyer, IBM Fellow, Microelectronics, IBM; Douglas Chen-Hua Yu, Senior Director of Integrated Interconnect and Packaging Division, TSMC, R&D Group; and Ho-Ming Tong, Chief R&D Officer & General Manager of Group R&D, ASE Group) were actually enthusiastic about recent events pointing to industrialization of 3D TSVs, and Iyer went so far as to proclaim “3D integration is logical extension of the holistic embedded memory roadmap and is big deal for heterogeneous integration.” In fact, when I heard Domic’s talk, my first thought was “ What? Did he not get the memo?”
Even the generally conservative Phil Garrou was excited about the progress we’ve made this year. “What we heard this week is what we’ve been waiting for the last few years,” he said. The events he was referring to was the trifecta of announcements since December 7: Samsung announced the development of an eight gigabyte (GB) registered dual inline memory module based on its advanced Green DDR3 DRAM that incorporates 3D TSVs; IBM and Semtech will develop a high-performance integrated ADC/DSP platform using IBM’s 3D silicon interposer technology using copper TSV interconnects; and Xilinx’ silicon stacking technology headed for production. All of these are expected to ramp into production in the 2011, 2012 time frame – aka, over the next year. In light of these events, Garrou noted that similar announcements will start coming fast and furious, with silicon interposers leading the charge. “Ultimately we believe 3D is the best in performance and density – however you can’t underestimate the potential and advantage of the interposers, they will always play an important role,” noted Yu.
Indeed, a show of hands in the room (or rather lack thereof) demonstrated that everyone thinks TSVs will be industrialized; a change from last year’s still somewhat skeptical view.
Here’s another thing I noticed; a year ago, the argument was that scaling is dead because although it’s possible to scale further, it’s really about engineering and that it is more costly than 3D TSV processes. This year, the story is the same but the message has changed. 3D is no longer an alternative to scaling, it’s a way to scale further. (I heard this at IEDM from various presenters, and again at the RTI event) It occurs to me the shift in approach is a way to get the front-end guys on board; they don’t have to give up on scaling, they just have to alter their perspective.
TSMC is certainly gung ho about the development of their back-end of line processes, although the “technical” presentation at IEDM 2011 was about as vague as I’ve ever seen. It went something like this: here are the “before” images of technical process challenges. Here are the “after” images showing TSMCs successful process optimization, but no reference to how, or what tools or materials would be used. Suffice it to say they’ve got it all under control. Guess we just have to believe them.
So what else was different about this year from last year? I’d say the solid representation from the EDA and test communities, as well as a better defined need for standards.
Last year, the EDA representatives who did present didn’t have a whole lot to show (save Lisa McIlrath, R3Logic, a 3D EDA pioneer); there was nothing to report from the test community; issues like thermal management were still an enigma; and no one could figure out how to standardize 3D, although it was thought there’d be a need for standards.
What a difference a year can make! We heard about test progress from Verigy’s Erik Volkrink, thermal solutions from Karl Geiser of General Dynamics Advanced Information Systems; and the panel discussion found its way to the standards discussion and stayed there — the overall perspective being that as difficult as 3D processes themselves are to standardize, standards for design rules, test, equipment, and handling are necessary and being addressed by both a SEMI task force and a SEMATECH 3D work group.
3-D IC silicon interposer design methodologies were also addressed by Vassilios Gerousis of Cadence and Damien Riquet, of STMicroelectronics. They’re combined message; its not just a matter of optimizing chips, you must also optimize the package and PCB, which calls for a multi-platform design methodology that involves system architecture and partitioning. That said, there is a complete ST/Cadence solution for TSV management. And Lisa McIlrath talked about optimal IP reuse for 3D stacks. Cost is still King. One way to control that says McIlrath, is to maximize IP reuse and find sweet spots in the cost.
Looking at the 3D system vs. 3D units is also critical. Dim-Lee Kwong, Executive Director, IME put it very succinctly saying, “We can integrate more than just IC in that cube. We have to think of promoting 3D Systems for the end user, because that’s what the end user cares about it, If we want it (3D) to take off, we have to pay attention to all those issues so that we can really integrate. If only a tiny part is integrated, it will not provide a full picture and the industry will NOT adopt 3D.”
Oh, and one final word about that 2.5D term being tossed around. What the heck is a half a dimension? Come on people, it’s all 3D, and it has arrived. Embrace it. – F.v.T.
