I was so busy making sure I have all the bios and presentations for the 3D sessions I’m chairing at this year’s IWLPC, which got underway today with its half-day tutorials, that I was LATE checking in on Southwest and ended up in the B group for boarding. I hate that. Last time that happened, I got stuck sitting next to a woman who’s son had a peanut allergy, so she had made sure that Southwest’s signature peanut snack was not being served. She also had an aversion to the sushi box I had brought on board for lunch and let it be known. I wanted to tell her she was lucky, I almost brought mixed nuts instead. But I kept it to myself.
In any case, I’m heading out tomorrow morning, and first on my list of duties is to introduce the kick-off speaker, Dr. Peter Ramm, Head of Si Technology and Vertical System Integration of the newly christened Fraunhofer Research Institution for Modular Solid State Technologies EMFT. The Munich branch of the Fraunhofer IZM was recently granted status as an independent research institution. I’m looking forward to learning more about that as well as the work Dr. Ramm is doing with process integration of heterogeneous systems, focusing on 3D integration.
I’m also excited about the rest of the 3D track, because every branch of the supply chain, from design and processes to reliability, inspection, test and standardization, is taking part. I’d also like to point out while the 3D technology supplier side is well represented (Alchimer, EV Group, SUSS, SET, Rudolph, Matech, Tessera, Vertical Circuits, FEI and Core Instruments) the research community also has a great turn-out for the 3D track with presenters (and sometimes multiple presenters) from IMEC, Fraunhofer, ITRI, North Carolina State University, LFI Leibniz University Hannover and Intel Asia-Pacific Research and Development.
3D-related topics spill over into the WLP track as well, where Seung Wook Yoon, STATS ChipPAC and Thorsten Mayer, Infineon will each talk about advancements in eWLB technology; and In-Soo Kang, Nepes Corp. will talk about a wafer-level embedded SiP for 3D. Richard Hollman of NEXX Systems will address chemistry and process parameters for Cu Pillars, which are also targeted for 3D stacking processes.
Over in the MEMS track, I’m hoping to get some insight for our upcoming discussion later this month, so that I ask intelligent questions of our panelists about the synergies between MEMS processes and 3D IC processes. EV Group’s Eric Pabo will be talking about best known practices for wafer bonding processes, and Bill Crouch of SUSS Microtec will talk about metal bonding alternatives to frit and anodic technologies. Also in the MEMS track, Jack Hoyd-Gigg Ng, of Heriot-Watt University will talk about development of innovative manufacturing methods for 3-dimensional WLP of ultrasonic transducers. That one seems to hit it all – WLP, 3D and MEMS.
So it’s time to post this and start packing. Talk to you next time! – F.v.T.
