I love field trips. This week, I took one over to historic old town Chandler, AZ, where IMAPS Arizona chapter was hosting a luncheon event at the Crown Point San Marcos Resort. (A year and a half in nearby Mesa, and I had never been beyond Chandler’s industrial parks.) I have to say, Amkor’s Lee Smith did a stellar job organizing this successful event. An impressive collection of table top exhibitors included EV Group, STATS ChipPAC, ASE, Amkor, Lord, ASM Pacific, Rogers, Finetech, and several others. The walk-in registration line extended out the door; everyone eager to hear Bob Lanzone’s presentation on Amkor’s latest achievement developed in close collaboration with Texas Instruments; fine-pitch copper pillar bumping technology.
Without revealing too many specific details, Lanzone gave enough away about this technology and the path Amkor and TI took to get there to make me sit up and listen. He called fine-pitch Cu pillar bumping an “industry game changing technology that will revolutionize packaging.” Ticking off the advantages, he said it this technology enables bump pitches of 50µm or less, is a lead-free solution, and is an extendable technology that will dovetail nicely into chip-on-chip (CoC) through silicon via (TSV) technology. (It was this last part that of course caught my attention most.)
Beyond the technology being a benchmark, Lanzone remarked that “to truly work with a customer in partnership with a defined goal and aggressive timeline was also benchmark.” This collaborative business development model allowed Amkor to work directly with a lead Alpha customer- in this case TI – to accelerate development and qualification. They were able to work without barriers and the whole process took less than two years from concept to qualified production, including developing the bump and packaging technology. Additionally, this structure required executive level commitment to the program, which translated into personnel commitment and focus, open technology sharing, and advanced silicon wafer material availability in terms of hundreds of wafers rather than five, explained Lanzone.
Currently, Lanzone said the technology is targeting 3 product applications —high performance processors; DSPs; and power management — with a dozen products already available for all three. They’re putting it into bare die and overmolded package-on-package (PoP) products, and the next-generation of TMV PoP will also put it to use. Lanzone also said the process has been demonstrated to 25µm bump pitch suitable for CoC and TSV in DRAM on logic applications.
In technology comparisons, Lanzone pointed out some significant advantages of fine-pitch Cu pillar bumps that included significant cost savings, reliability, performance, formfactor, and most importantly from an R&D investment perspective, extendibility of the technology.
“The good thing about this technology development is that everything we’re doing here can be done with TSV. We have the assembly side down. Its’ the wafer processing side that still need work,” noted Lanzone. “When the front end guys work out the wafer processing for TSV, we can take the complete TSV wafers and apply this in the back end.”
Wow. Did you hear that foundries? Better get cracking. You’re holding up the line. – F.v.T.
