Sometimes I like to mix it up a bit. So last night I was the invited guest speaker at the BiTS workshop, an event focused on the latest information about burn-in and test socketing, as well as semiconductor test issues. I was asked to share what I know about 3D packaging, and particularly 3D TSV test issues. I hope I did justice to our collective cause! Today I spent the day as a roving reporter for the event, interviewing the other invited speakers for broadcast on the event’s new virtual expo, vBiTS. As it happens, I gathered a few bits of information might be of interest to the 3D InCites members.
First up was Ken Butler, Fellow at Texas Instruments, who talked about adaptive test versus traditional test, and how it’s really suited to all the variable devices that need to be tested in today’s world- including 3D configurations. Rather than just performing one-off test to make rapid decisions, adaptive allows for data acquisition, movement and analysis. While adaptive test doesn’t eliminate the need for burn-in, it optimizes its use. In some cases it equals test time reduction, but more importantly it allows you to learn as much as possible from each wafer in terms of process learning, device debugging, and quality improvement.
When I asked Butler the million dollar question, will test solutions be ready for 3D TSVs, he unfortunately agreed with Al Crouch, whose prediction was “No”, but the good news is that efforts are now underway. We talked about the importance of collaboration across the supply chain, and sharing information. He noted that even the IDMS are seeing the need to collaborate across company boundaries to get this done. That’s what I like to hear!
I also spoke with Brandon Prior, who, incidentally, will also be keynote tomorrow at IMAPS Device Packaging Conference. His talk at BiTS was focused on low cost packaging and small form factor package, offering suggestions on how to reduce manufacturing and production costs on mostly main-stream packages; however he did make a point of mentioning 3D TSVs in his value trend chart. Although the 10% market share of $60B by 2020 he predicts may seem conservative, he explained that’s taking into consideration starting from 0%, and to go from $0 to $10B in 9 years is a pretty significant climb. Cost effective test is still lacking for 3D TSV, he noted.
Tom Di Stefano, of Centipede Systems addressed the rising cost of test overall, noting that the back-end guys could learn something from the front end guys with regard to automation. His company is developing a test-in-tray technology that he says allows continuous carrier and handling from the time the wafer is diced through final test which could be good news for the 3D TSV manufacturers looking for ways to address a 3D test flow that involves testing before and after thinning, TSV formation, and at each stacking phase. The test-in-tray concept, still in development stages, offers a possible solution when considering die-to-die stacking processes.
Speaking of sharing information, I also came away with some questions for you from the socket guys, who could use some guidance of what will be required for final testing of 3D ICs. It’s assumed there will still be a need for burn-in and final test. Can current socket configurations handle the 3D ICs with TSVs? Will the pressure from the Z-direction for burn-in damage the final stack? If you know the answers to these questions, please share them here. F.v.T.
